// ****************************************************************************************** // Project : STM32F042K6T6 Sample Program // Program Name : // Programer : // Create date : Version 1.0 H30.07.17 // History : // Laungage : Atollic TrueSTDIO C Launguage // ****************************************************************************************** // Description // ****************************************************************************************** #include "stm32f0xx.h" #include "stddef.h" void Init_clock(unsigned char); void Timer(void); void Wait(unsigned int); #define PI_HSI_SYSCLK 1 //HSI clock selected #define PI_HSE_SYSCLK 2 //HSE clock selected #define PI_PLL_SYSCLK 3 //PLL clock selected int main(void) { // ******************* // 1.Initialize // ******************* // (1)Define Clock Init_clock(PI_HSI_SYSCLK); // HSI clock //Init_clock(PI_HSE_SYSCLK); // HSE clock //Init_clock(PI_PLL_SYSCLK); // PLL clock // (2)Setting Timer1 RCC->APB2ENR = 0x0800; // APB2ENR[11]:TIM1EN TIM1 Timer clock enable // (3)Define Port RCC->AHBENR |= 0x00040000; // Setting GPIO GPIOB->MODER |= 0x0004; // Direction PB1 // ******************* // 2.Program main // ******************* while(1){ GPIOB->ODR = 0x0002; Wait(1); GPIOB->ODR = 0x0000; Wait(1); } } //****************************************************************************************** // Function Name : Init_clock // Title : Initialized System clock // Input : // Output : // Description : STM32F0x1/STM32F0x2/STM32F0x8 Version //****************************************************************************************** void Init_clock(unsigned char clk_mode) { // ***************************************** // RCC_CFGR(Clock configuration register) Address offset: 0x04 / Reset value: 0x0000 0000 // ***************************************** // [31] PLLNODIV: PLL clock not divided for MCO (not available on STM32F05x devices) // This bit is set and cleared by software. It switches off divider by 2 for PLL connection to MCO. // 0: PLL is divided by 2 for MCO // 1: PLL is not divided for MCO // [30:28] MCOPRE[2:0]: Microcontroller Clock Output Prescaler (not available on STM32F05x // devices) // These bits are set and cleared by software to select the MCO prescaler division factor. To // avoid glitches, it is highly recommended to change this prescaler only when the MCO output is // disabled. // 000: MCO is divided by 1 // 001: MCO is divided by 2 // 010: MCO is divided by 4 // ..... // 111: MCO is divided by 128 // [27:24] MCO[3:0]: Microcontroller clock output // Set and cleared by software. // 0000: MCO output disabled, no clock on MCO // 0001: Internal RC 14 MHz (HSI14) oscillator clock selected // 0010: Internal low speed (LSI) oscillator clock selected // 0011: External low speed (LSE) oscillator clock selected // 0100: System clock selected // 0101: Internal RC 8 MHz (HSI) oscillator clock selected // 0110: External 4-32 MHz (HSE) oscillator clock selected // 0111: PLL clock selected (divided by 1 or 2, depending on PLLNODIV) // 1000: Internal RC 48 MHz (HSI48) oscillator clock selected // Note: This clock output may have some truncated cycles at startup or during MCO clock // source switching. // [23:22] Reserved, must be kept at reset value. // // [21:18] PLLMUL[3:0]: PLL multiplication factor // These bits are written by software to define the PLL multiplication factor. These bits can be // written only when PLL is disabled. // Caution: The PLL output frequency must not exceed 48 MHz. // 0000: PLL input clock x 2 // 0001: PLL input clock x 3 // 0010: PLL input clock x 4 // 0011: PLL input clock x 5 // 0100: PLL input clock x 6 // 0101: PLL input clock x 7 // 0110: PLL input clock x 8 // 0111: PLL input clock x 9 // 1000: PLL input clock x 10 // 1001: PLL input clock x 11 // 1010: PLL input clock x 12 // 1011: PLL input clock x 13 // 1100: PLL input clock x 14 // 1101: PLL input clock x 15 // 1110: PLL input clock x 16 // 1111: PLL input clock x 16 // [17] PLLXTPRE: HSE divider for PLL input clock // This bit is the same bit as bit PREDIV[0] from RCC_CFGR2. Refer to RCC_CFGR2 PREDIV // bits description for its meaning. // [16:15] PLLSRC[1:0]: PLL input clock source // Set and cleared by software to select PLL or PREDIV clock source. These bits can be written // only when PLL is disabled. // 00: HSI/2 selected as PLL input clock (PREDIV forced to divide by 2 on STM32F04x, // STM32F07x and STM32F09x devices) // 01: HSI/PREDIV selected as PLL input clock // 10: HSE/PREDIV selected as PLL input clock // 11: HSI48/PREDIV selected as PLL input clock // Note: Bit PLLSRC[0] is available only on STM32F04x, STM32F07x and STM32F09x // devices, otherwise it is reserved (with value zero). // [14] ADCPRE: ADC prescaler // Obsolete setting. Proper ADC clock selection is done inside the ADC_CFGR2 (refer to // Section 13.12.5: ADC configuration register 2 (ADC_CFGR2) on page 263). // [13:11] Reserved, must be kept at reset value. // [10:8] PPRE[2:0]: PCLK prescaler // Set and cleared by software to control the division factor of the APB clock (PCLK). // 0xx: HCLK not divided // 100: HCLK divided by 2 // 101: HCLK divided by 4 // 110: HCLK divided by 8 // 111: HCLK divided by 16 // [7:4] HPRE[3:0]: HCLK prescaler // Set and cleared by software to control the division factor of the AHB clock. // 0xxx: SYSCLK not divided // 1000: SYSCLK divided by 2 // 1001: SYSCLK divided by 4 // 1010: SYSCLK divided by 8 // 1011: SYSCLK divided by 16 // 1100: SYSCLK divided by 64 // 1101: SYSCLK divided by 128 // 1110: SYSCLK divided by 256 // 1111: SYSCLK divided by 512 // [3:2] SWS[1:0]: System clock switch status // Set and cleared by hardware to indicate which clock source is used as system clock. // 00: HSI oscillator used as system clock // 01: HSE oscillator used as system clock // 10: PLL used as system clock // 11: HSI48 oscillator used as system clock (when available) // [1:0] SW[1:0]: System clock switch // Set and cleared by software to select SYSCLK source. // Cleared by hardware to force HSI selection when leaving Stop and Standby mode or in case // of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security // System is enabled). // 00: HSI selected as system clock // 01: HSE selected as system clock // 10: PLL selected as system clock // 11: HSI48 selected as system clock (when available) switch (clk_mode){ case PI_HSI_SYSCLK : RCC->CFGR = 0x00000000; break; case PI_HSE_SYSCLK : RCC->CFGR = 0x00000001; break; case PI_PLL_SYSCLK : RCC->CFGR = 0x0008000A; break; default: RCC->CFGR = 0x00000000; } } //****************************************************************************************** // Function Name : Wait function // Title : Wait 1[S] * n // Input : // Output : // Description : STM32F0x1/STM32F0x2/STM32F0x8 Version //****************************************************************************************** void Wait(unsigned int i) { unsigned int lp; for(lp=0;lp 1Hz(1S) // Description 2 : STM32F0x1/STM32F0x2/STM32F0x8 Version //****************************************************************************************** void Timer(void) { // ********************************* // TIM1_CNT(TIM1 Counter) // ********************************* TIM1->CNT = 0x0000; // ********************************* // TIM1_PSC(TIM1 Prescaler) // ********************************* // // 8[MHz] / 0d800[0x320](Prescaler) ==> 10[KHz] // 24[MHz] / 0d2400[0x960](Prescaler) ==> 10[KHz] // 64[MHz] / 0d6400[0x1900](Prescaler) ==> 10[KHz] // // TIM1->PSC = 0x0960; // TIM1->PSC = 0x1900; TIM1->PSC = 0x0320; // ********************************* // TIM1_ARR(TIM1 Auto-reload register) // ********************************* // // 10KHz / 0d10000[0x2710](ARR) ==> 1[S] // TIM1->ARR = 0x2710; // ********************************* // TIM1_CR1(Control register 1) Reset value: 0x00 // ********************************* // TIM1_CR1[15:10] Reserved, always read as 0 // TIM1_CR1[9:8] CKD[1:0]: Clock division // TIM1_CR1[7] ARPE: Auto-reload preload enable // TIM1_CR1[6:5] CMS[1:0]: Center-aligned mode selection // TIM1_CR1[4] DIR: Direction // 0: Counter used as up-counter // 1: Counter used as down-counter // TIM1_CR1[3] OPM: One-pulse mode // 0: Counter is not stopped at update event // 1: Counter stops counting at the next update event (clearing the CEN bit) // TIM1_CR1[2] URS: Update request source // TIM1_CR1[1] UDIS: Update disable. // TIM1_CR1[0] CEN: Counter enable // 0: Counter disabled // 1: Counter enabled TIM1->CR1 = 0x0001; // ********************************* // TIM1_SR(Status register) // ********************************* // TIM1_SR[15:13] Reserved, always read as 0. // TIM1_SR[12] CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description // TIM1_SR[11] CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description // TIM1_SR[10] CC2OF: Capture/Compare 2 overcapture flag refer to CC1OF description // TIM1_SR[9] CC1OF: Capture/Compare 1 overcapture flag // This flag is set by hardware only when the corresponding channel is configured in input // 0: No overcapture has been detected. // 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set // TIM1_SR[8] Reserved, always read as 0. // TIM1_SR[7] BIF: Break interrupt flag // TIM1_SR[6] TIF: Trigger interrupt flag // TIM1_SR[5] COMIF: Commutation interrupt flag // TIM1_SR[4] CC4IF: Capture/compare 4 interrupt flag // TIM1_SR[3] CC3IF: Capture/compare 3 interrupt flag // TIM1_SR[2] CC2IF: Capture/compare 2 interrupt flag // TIM1_SR[1] CC1IF: Capture/compare 1 interrupt flag // If channel CC1 is configured as output: // This flag is set by hardware when the counter matches the compare value, with some exception in // center-aligned mode (refer to the CMS bits from TIM1_CR1 register description). // It is cleared by software. // 0: No match // 1: The content of the counter register TIM1_CNT matches the content of the TIM1_CCR1 register // If channel CC1 is configured as input: // This bit is set by hardware on a capture. // It is cleared by software or by reading the TIM1_CCR1L register. // 0: No input capture has occurred // 1: The counter value has been captured in the TIM1_CCR1 register (an edge has been detected on // IC1 which matches the selected polarity). // TIM1_SR[0] UIF: Update interrupt flag // This bit is set by hardware on an update event. It is cleared by software. // 0: No update occurred. // 1: Update interrupt pending. This bit is set by hardware when the registers are updated: // -At overflow or underflow regarding the repetition counter value (update if repetition // counter = 0) and if the UDIS=0 in the TIMx_CR1 register. // -When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 // and UDIS=0 in the TIMx_CR1 register. TIM1->SR &= 0xFFFE; //Clear UIF bit while((TIM1->SR & 0x0001)==0); //Check UIF flag TIM1->CR1 &= 0xFFFE; //Counter disabled }