// ******************************************************************************************
//   Project      :  STM32F103C8T6 Sample Program
//   Program Name :
//   Programer    :
//   Create date  :  Version 1.0    H30.07.17
//   History      :
//   Laungage     :  Atollic TrueSTDIO C Launguage
// ******************************************************************************************
//   Description
//        LED : C13
//        SW0 : B0
// ******************************************************************************************
#include <stddef.h>
#include <stdio.h>
#include "stm32f10x.h"

#define PI_HSI_SYSCLK   1    //HSI clock selected
#define PI_HSE_SYSCLK   2    //HSE clock selected
#define PI_PLL_SYSCLK   3    //PLL clock selected

void Timer(void);
void Wait(unsigned int);
void Init_clock(unsigned char);

int main(void)
{

//  Init_clock(PI_PLL_SYSCLK); //PLL 64MHz (8MHz * 8)
//  Init_clock(PI_HSI_SYSCLK); //Internal 8MHz RC oscillator
    Init_clock(PI_HSE_SYSCLK); //External 8MHz Crystal

    RCC->APB2ENR = 0x0010;     // APB2ENR[2-3]:IOPC   I/O port C clock enable
    RCC->APB2ENR = 0x0810;     // APB2ENR[2-3]:IOPC   I/O port C clock enable
                               // APB2ENR[11]:TIM1EN           TIM1 Timer clock enable
    RCC->APB2ENR |= 0x00000008;// APB2ENR[3]:IOPB clock enable

    GPIOB->CRL  = 0x44444444;  // Port configuration register low (GPIOn[0-7])
                               // PORTB[ALL]Input mode (Reset state) / Floating input (Reset state)

//  GPIOC->CRL                 // Port configuration register low (GPIOn[0-7])
    GPIOC->CRH  = 0x44144444;  // Port configuration register high(GPIOn[8-15])
    GPIOC->ODR  = 0x00002000;  // LED OFF(PORTC[13] High)

    while(1){
    	if((0b1 & GPIOB->IDR ) == 0) GPIOC->ODR = 0x00002000;
    	else                         GPIOC->ODR = 0x00000000;
    }
}

//******************************************************************************************
//   Function Name : Init_clock
//   Title         : Initialized System clock
//   Input         :
//   Output        :
//   Description   :
//******************************************************************************************
void Init_clock(unsigned char clk_mode)
{

    switch (clk_mode){
        case  PI_HSI_SYSCLK : RCC->CFGR = 0x00000000;
            break;
        case  PI_HSE_SYSCLK : RCC->CFGR = 0x00000001;
            break;
        case  PI_PLL_SYSCLK : RCC->CFGR = 0x00000002;
            break;
        default:              RCC->CFGR = 0x00000000;
    }

    return;

// 2.Set PLL
    RCC->CR   &= 0xFDFFFFFF;
    RCC->CR   &= 0xFEFFFFFF;
    RCC->CFGR |= 0x00190000;
    RCC->CR   |= 0x01000000;
}

//******************************************************************************************
//   Function Name : Wait
//   Title         :
//   Input         :
//   Output        :
//   Description   :
//******************************************************************************************
void Wait(unsigned int i)
{
	unsigned int lp;
    for(lp=0;lp<i;lp++){
	    Timer();
    }
}

//******************************************************************************************
//   Function Name : Timer
//   Title         : Wait 1[S]
//   Input         :
//   Output        :
//   Description   :
//******************************************************************************************
void Timer(void)
{
// *********************************
// TIM1_CNT(TIM1 Counter)
// *********************************
    TIM1->CNT = 0x0000;

// *********************************
// TIM1_PSC(TIM1 Prescaler)
// *********************************
//
//      8[MHz] /  0d800[0x320](Prescaler)  ==> 10[KHz]
//     24[MHz] / 0d2400[0x960](Prescaler)  ==> 10[KHz]
//     64[MHz] / 0d6400[0x1900](Prescaler) ==> 10[KHz]
//
//  TIM1->PSC = 0x0960;
//  TIM1->PSC = 0x1900;
    TIM1->PSC = 0x0320;

// *********************************
//  TIM1_ARR(TIM1 Auto-reload register)
// *********************************
//
//      10KHz / 0d10000[0x2710](ARR) ==> 1[S]
//
    TIM1->ARR = 0x2710;

    // *********************************
// TIM1_CR1(Control register 1)     Reset value: 0x00
// *********************************
//     TIM1_CR1[15:10] Reserved, always read as 0
//     TIM1_CR1[9:8] CKD[1:0]: Clock division
//     TIM1_CR1[7] ARPE: Auto-reload preload enable
//     TIM1_CR1[6:5] CMS[1:0]: Center-aligned mode selection
//     TIM1_CR1[4] DIR: Direction
//           0: Counter used as up-counter
//           1: Counter used as down-counter
//     TIM1_CR1[3] OPM: One-pulse mode
//           0: Counter is not stopped at update event
//           1: Counter stops counting at the next update event (clearing the CEN bit)
//     TIM1_CR1[2] URS: Update request source
//     TIM1_CR1[1] UDIS: Update disable.
//     TIM1_CR1[0] CEN: Counter enable
//           0: Counter disabled
//           1: Counter enabled
    TIM1->CR1 = 0x0001;

// *********************************
// TIM1_SR(Status register)
// *********************************
//      TIM1_SR[15:13] Reserved, always read as 0.
//      TIM1_SR[12] CC4OF: Capture/Compare 4 overcapture flag     refer to CC1OF description
//      TIM1_SR[11] CC3OF: Capture/Compare 3 overcapture flag     refer to CC1OF description
//      TIM1_SR[10] CC2OF: Capture/Compare 2 overcapture flag     refer to CC1OF description
//      TIM1_SR[9] CC1OF: Capture/Compare 1 overcapture flag
//             This flag is set by hardware only when the corresponding channel is configured in input
//                0: No overcapture has been detected.
//                1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
//      TIM1_SR[8] Reserved, always read as 0.
//      TIM1_SR[7] BIF: Break interrupt flag
//      TIM1_SR[6] TIF: Trigger interrupt flag
//      TIM1_SR[5] COMIF: Commutation interrupt flag
//      TIM1_SR[4] CC4IF: Capture/compare 4 interrupt flag
//      TIM1_SR[3] CC3IF: Capture/compare 3 interrupt flag
//      TIM1_SR[2] CC2IF: Capture/compare 2 interrupt flag
//      TIM1_SR[1] CC1IF: Capture/compare 1 interrupt flag
//          If channel CC1 is configured as output:
//               This flag is set by hardware when the counter matches the compare value, with some exception in
//               center-aligned mode (refer to the CMS bits from TIM1_CR1 register description).
//               It is cleared by software.
//                   0: No match
//                   1: The content of the counter register TIM1_CNT matches the content of the TIM1_CCR1 register
//          If channel CC1 is configured as input:
//               This bit is set by hardware on a capture.
//               It is cleared by software or by reading the TIM1_CCR1L register.
//                   0: No input capture has occurred
//                   1: The counter value has been captured in the TIM1_CCR1 register (an edge has been detected on
//                      IC1 which matches the selected polarity).
//      TIM1_SR[0] UIF: Update interrupt flag
//               This bit is set by hardware on an update event. It is cleared by software.
//                   0: No update occurred.
//                   1: Update interrupt pending. This bit is set by hardware when the registers are updated:
//                       -At overflow or underflow regarding the repetition counter value (update if repetition
//                        counter = 0) and if the UDIS=0 in the TIMx_CR1 register.
//                       -When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0
//                        and UDIS=0 in the TIMx_CR1 register.

    TIM1->SR &= 0xFFFE;                        //Clear UIF bit
    while((TIM1->SR & 0x0001)==0);             //Check UIF flag

    TIM1->CR1 &= 0xFFFE;                        //Counter disabled

}