// ****************************************************************************************** // Project : STM32VLDISCOVERY Sample Program (STM32F100RB) // Program Name : // Programer : // Create date : Version 1.0 H24.10.08 // History : // Laungage : Atollic TrueSTDIO C Launguage // ****************************************************************************************** // Description // On board LED : PC8, PC9 // MCO(The microcontroller clock output) : PA8 // ****************************************************************************************** #include #include "stm32f10x.h" void Clock_OUT(unsigned char); #define PI_SYS_OUT 1 //System clock (SYSCLK) selected #define PI_HSI_OUT 2 //HSI clock selected #define PI_HSE_OUT 3 //HSE clock selected #define PI_PLL_OUT 4 //PLL clock divided by 2 selected int main(void) { // ******************* // 1.Initialize // ******************* // (1)Define APB2(peripheral clock enable register) RCC->APB2ENR = 0x0005; // APB2ENR[2]:IOPAEN, APB2ENR[0]:AFIOEN I/O port A clock enable, Alternate function I/O clock enable // Set and cleared by software. 0: I/O portn clock disabled, 1:I/O portn clock enabled // (2)Define I/O Port A GPIOA->CRL = 0x44444444; // Port configuration register low (GPIOA[0-7]) GPIOA->CRH = 0x4444444B; // Port configuration register high(GPIOA[8-15]) // B: CNF=10:Alternate function output Push-pull, MODE=11:Output mode, max speed 50 MHz. // 4: CNF=01:Floating input (reset state), MODE=00:Input mode (reset state) // GPIOA->IDR // Port input data register (Read Only) IDR[31-16]:Reserved,@IDR[15-0]:Port output data // GPIOA->ODR // Port output data register ODR[31-16]:Reserved,@ODR[15-0]:Port output data // GPIOA->BSRR // Port bit set/reset registe // GPIOA->BRR // Port bit reset register // GPIOA->LCKR // Port configuration lock register // (3)Clock output // Clock_OUT(PI_SYS_OUT); //Default 8[MHz] : // Clock_OUT(PI_HSI_OUT); //Default 8[MHz] : 8MHz Inrenal RC // Clock_OUT(PI_HSE_OUT); //Default 8.00[MHz] : 8MHz Crystal Clock_OUT(PI_PLL_OUT); //Default 12.00[MHz] : 24MHz / 2 (divided by 2) // ******************* // 2.Program main // ******************* while(1); } //**************************************************************************** // Function Name : Clock_OUT // Title : // Input : // Output : // Description : //**************************************************************************** void Clock_OUT(unsigned char out_mode) { // ***************************************** // RCC_CFGR(Clock configuration register) Reset value: 0x0000 0000 // ***************************************** // RCC_CFGR[31:27] Reserved, always read as 0. // RCC_CFGR[26:24] MCO: Microcontroller clock output // Set and cleared by software. // 0xx: No clock // 100: System clock (SYSCLK) selected // 101: HSI clock selected // 110: HSE clock selected // 111: PLL clock divided by 2 selected // This clock output may have some truncated cycles at startup or during MCO clock source switching. // RCC_CFGR[23:22] Reserved. // RCC_CFGR[21:18] PLLMUL: PLL multiplication factor // These bits are written by software to define the PLL multiplication factor. // These bits can be written only when PLL is disabled. // Caution: The PLL output frequency must be in the 16-24 MHz range. // 0000: PLL input clock x 2 // 0001: PLL input clock x 3 // 0010: PLL input clock x 4 // 0011: PLL input clock x 5 // 0100: PLL input clock x 6 // 0101: PLL input clock x 7 // 0110: PLL input clock x 8 // 0111: PLL input clock x 9 // 1000: PLL input clock x 10 // 1001: PLL input clock x 11 // 1010: PLL input clock x 12 // 1011: PLL input clock x 13 // 1100: PLL input clock x 14 // 1101: PLL input clock x 15 // 1110: PLL input clock x 16 // 1111: PLL input clock x 16 // RCC_CFGR[17] PLLXTPRE: LSB of division factor PREDIV1 // Set and cleared by software to select the least significant bit of the PREDIV1 division factor. // It is the same bit as bit 0 in the RCC_CFGR2 register, so modifying bit 0 in the RCC_CFGR2 register changes this bit accordingly. // If bits[3:1] in the RCC_CFGR2 register are not set, the PLLXTPRE bit controls if PREDIV1 divides its input clock by 2 (PLLXTPRE=1) or not (PLLXTPRE=0). // This bit can be written only when the PLL is disabled. // RCC_CFGR[16] PLLSRC: PLL entry clock source // Set and cleared by software to select PLL clock source. // This bit can be written only when PLL is disabled. // 0: HSI oscillator clock / 2 selected as PLL input clock // 1: Clock from PREDIV1 selected as the PLL input clock // RCC_CFGR[15:14] ADCPRE: ADC prescaler // Set and cleared by software to select the frequency of the clock to ADC1. // 00: PLCK2 divided by 2 // 01: PLCK2 divided by 4 // 10: PLCK2 divided by 6 // 11: PLCK2 divided by 8 // RCC_CFGR[13:11] PPRE2: APB high-speed prescaler (APB2) // Set and cleared by software to control the division factor of the APB high-speed clock (PCLK2). // 0xx: HCLK not divided // 100: HCLK divided by 2 // 101: HCLK divided by 4 // 110: HCLK divided by 8 // 111: HCLK divided by 16 // RCC_CFGR[10:8] PPRE1: APB low-speed prescaler (APB1) // Set and cleared by software to control the division factor of the APB low-speed clock (PCLK1). // Warning: the software has to set correctly these bits to not exceed 36 MHz on this domain. // 0xx: HCLK not divided // 100: HCLK divided by 2 // 101: HCLK divided by 4 // 110: HCLK divided by 8 // 111: HCLK divided by 16 // RCC_CFGR[7:4] HPRE: AHB prescaler // Set and cleared by software to control the division factor of the AHB clock. // 0xxx: SYSCLK not divided // 1000: SYSCLK divided by 2 // 1001: SYSCLK divided by 4 // 1010: SYSCLK divided by 8 // 1011: SYSCLK divided by 16 // 1100: SYSCLK divided by 64 // 1101: SYSCLK divided by 128 // 1110: SYSCLK divided by 256 // 1111: SYSCLK divided by 512 // RCC_CFGR[3:2] SWS: System clock switch status // Set and cleared by hardware to indicate which clock source is used as system clock. // 00: HSI oscillator used as system clock // 01: HSE oscillator used as system clock // 10: PLL used as system clock // 11: not applicable // RCC_CFGR[1:0] SW: System clock switch // Set and cleared by software to select SYSCLK source. // Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of // failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). // 00: HSI selected as system clock // 01: HSE selected as system clock // 10: PLL selected as system clock // 11: not allowed switch (out_mode){ case PI_SYS_OUT : RCC->CFGR = 0x04000000; break; case PI_HSI_OUT : RCC->CFGR = 0x05000000; break; case PI_HSE_OUT : RCC->CFGR = 0x06000000; break; case PI_PLL_OUT : RCC->CFGR = 0x07000000; break; default: RCC->CFGR = 0x00000000; } }