--******************************************************************************************
--  Cyclone2 Sample Program
--   Project      :
--   Program Name :
--   Programer    :
--   Create date  :  Version 1.0    R04.10.01
--   History      :
--   Laungage     :  VHDL (ALTERA Quartus2 Version 13.0) 
--******************************************************************************************
--   Description
--
--******************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TEST0001 is
    Port ( LED_0 : out  STD_LOGIC;
           LED_1 : out  STD_LOGIC;
           LED_2 : out  STD_LOGIC;
           IN_SW : in   STD_LOGIC);
end TEST0001;

architecture Behavioral of TEST0001 is

begin
   LED_0 <= IN_SW ;
   LED_1 <= IN_SW ;
   LED_2 <= IN_SW ;
end Behavioral;