--******************************************************************************************
--  Cyclone2 Sample Program
--   Project      :
--   Program Name :
--   Programer    :
--   Create date  :  Version 1.0    R04.10.07
--   History      :
--   Laungage     :  VHDL (ALTERA Quartus2 Version 13.0) 
--******************************************************************************************
--   Description
--
--******************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TEST0002 is
    Port ( LED_0 : out  STD_LOGIC;
           LED_1 : out  STD_LOGIC;			  
           IN_SW : in   STD_LOGIC);
end TEST0002;

ARCHITECTURE rtl of TEST0002 IS
  COMPONENT TESTCNT
  PORT(
    CLK  : IN std_logic;
    ANS0 : out std_logic;
    ANS1 : out std_logic
  );
  END COMPONENT;
  
BEGIN
    COUNT1 : TESTCNT port map(
        CLK  => IN_SW,	 
        ANS0 => LED_0,
        ANS1 => LED_1
    ); 
	 
END rtl;

--******************************************************************************************
-- Function 1
--******************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TESTCNT IS
  PORT(
    CLK  : IN std_logic;
    ANS0 : out std_logic; 
    ANS1 : out std_logic
    );
END TESTCNT;

ARCHITECTURE rtl of TESTCNT IS
    SIGNAL counter : integer range 0 to 50000000;
    SIGNAL ans_1   : std_LOGIC;	 
BEGIN
    PROCESS(CLK)
    BEGIN
        if(CLK'event and CLK='1') then
            counter <= counter + 1;		  
            if( counter = 49999999 ) then
                ans_1 <= not ans_1;
                counter <= 0;		
            end if;					 
        end if;
    END PROCESS;      
    ANS0 <= ANS_1;
    ANS1 <= not ANS_1;	 
end rtl;