library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity COMPARE_HEX is
    port( 
        IN_0     : in std_logic;
        IN_1     : in std_logic;
        IN_2     : in std_logic;
        IN_3     : in std_logic;
        IN_4     : in std_logic;
        IN_5     : in std_logic;
        IN_6     : in std_logic;
        IN_7     : in std_logic;
        IN_8     : in std_logic;
        IN_9     : in std_logic;
        IN_10    : in std_logic;
        IN_11    : in std_logic;
        IN_12    : in std_logic;
        IN_13    : in std_logic;
        IN_14    : in std_logic;
        IN_15    : in std_logic;
        IN_16    : in std_logic;
        IN_17    : in std_logic;
        IN_18    : in std_logic;
        IN_19    : in std_logic;
        IN_20    : in std_logic;
        IN_21    : in std_logic;
        IN_22    : in std_logic;
        IN_23    : in std_logic;
        IN_24    : in std_logic;
        CLK      : in std_logic;
        OUT_CLK  : out std_logic
    );
end COMPARE_HEX;

architecture rtl of COMPARE_HEX is
    signal number_0  : std_logic_vector(24 downto 0); 
    signal counter_0 : std_logic_vector(24 downto 0);
    signal out_stat  : std_logic;
begin
    number_0(0)  <= IN_0;
    number_0(1)  <= IN_1;
    number_0(2)  <= IN_2;
    number_0(3)  <= IN_3;
    number_0(4)  <= IN_4;
    number_0(5)  <= IN_5;
    number_0(6)  <= IN_6;
    number_0(7)  <= IN_7;
    number_0(8)  <= IN_8;
    number_0(9)  <= IN_9;
    number_0(10) <= IN_10;
    number_0(11) <= IN_11;
    number_0(12) <= IN_12;
    number_0(13) <= IN_13;
    number_0(14) <= IN_14;
    number_0(15) <= IN_15;
    number_0(16) <= IN_16;
    number_0(17) <= IN_17;
    number_0(18) <= IN_18;
    number_0(19) <= IN_19;
    number_0(20) <= IN_20;
    number_0(21) <= IN_21;
    number_0(22) <= IN_22;
    number_0(23) <= IN_23;
    number_0(24) <= IN_24;

    process(CLK)
    begin
        if(CLK'event and CLK='1') then
            if( counter_0 = number_0 ) then
                counter_0 <= CONV_STD_LOGIC_VECTOR(0,25);
                if( out_stat = '1' ) then
                    out_stat <= '0';
                    OUT_CLK  <= '0';
                else 
                    out_stat <= '1';
                    OUT_CLK  <= '1';
                end if;
            else 
                counter_0 <= counter_0 + 1;
            end if;					 
        end if;
    end process; 
end rtl;