--****************************************************************************************** -- MAX2 Sample Program -- Project : -- Program Name : -- Programer : -- Create date : Version 1.0 H24.12.18 -- History : -- Laungage : VHDL (ALTERA Quartus2 Version 8.1) --****************************************************************************************** -- Description -- --****************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SAMPLE01 is Port( IN_MODE : in std_logic; IN_CLK : in std_logic; IN_DATA : in std_logic; SYS_CLK : in std_logic; ADC_0 : out STD_LOGIC; ADC_1 : out STD_LOGIC; ADC_2 : out STD_LOGIC; ADC_3 : out STD_LOGIC; ADC_4 : out STD_LOGIC; ADC_5 : out STD_LOGIC; ADC_6 : out STD_LOGIC; ADC_7 : out STD_LOGIC ); end SAMPLE01; architecture rtl of SAMPLE01 is component SETDATA PORT( MODE : in std_logic; CLK : in std_logic; DATA : in std_logic; Q0 : out std_logic; Q1 : out std_logic; Q2 : out std_logic; Q3 : out std_logic; Q4 : out std_logic; Q5 : out std_logic; Q6 : out std_logic; Q7 : out std_logic; Q8 : out std_logic; Q9 : out std_logic; Q10 : out std_logic; Q11 : out std_logic; Q12 : out std_logic; Q13 : out std_logic; Q14 : out std_logic; Q15 : out std_logic; Q16 : out std_logic; Q17 : out std_logic; Q18 : out std_logic; Q19 : out std_logic; Q20 : out std_logic; Q21 : out std_logic; Q22 : out std_logic; Q23 : out std_logic; Q24 : out std_logic); end component; component COMPARE_HEX PORT( IN_0 : in std_logic; IN_1 : in std_logic; IN_2 : in std_logic; IN_3 : in std_logic; IN_4 : in std_logic; IN_5 : in std_logic; IN_6 : in std_logic; IN_7 : in std_logic; IN_8 : in std_logic; IN_9 : in std_logic; IN_10 : in std_logic; IN_11 : in std_logic; IN_12 : in std_logic; IN_13 : in std_logic; IN_14 : in std_logic; IN_15 : in std_logic; IN_16 : in std_logic; IN_17 : in std_logic; IN_18 : in std_logic; IN_19 : in std_logic; IN_20 : in std_logic; IN_21 : in std_logic; IN_22 : in std_logic; IN_23 : in std_logic; IN_24 : in std_logic; CLK : in std_logic; OUT_CLK : out std_logic ); end component; signal cmp_data : std_logic_vector(24 downto 0); signal out_clk : std_logic; signal tmp_line : std_logic_vector(7 downto 0); signal data_index : std_logic_vector(7 downto 0); subtype data_val is std_logic_vector(7 downto 0); type data_val_array is array (0 to 199) of data_val; constant SIN_DATA : data_val_array := ( "01100100","01100111","01101010","01101101","01110001","01110100","01110111","01111010","01111101","10000000", "10000011","10000110","10001001","10001100","10001111","10010001","10010100","10010111","10011010","10011100", "10011111","10100001","10100100","10100110","10101000","10101011","10101101","10101111","10110001","10110011", "10110101","10110111","10111000","10111010","10111100","10111101","10111110","11000000","11000001","11000010", "11000011","11000100","11000101","11000110","11000110","11000111","11000111","11001000","11001000","11001000", "11001000","11001000","11001000","11001000","11000111","11000111","11000110","11000110","11000101","11000100", "11000011","11000010","11000001","11000000","10111110","10111101","10111100","10111010","10111000","10110111", "10110101","10110011","10110001","10101111","10101101","10101011","10101000","10100110","10100100","10100001", "10011111","10011100","10011010","10010111","10010100","10010001","10001111","10001100","10001001","10000110", "10000011","10000000","01111101","01111010","01110111","01110100","01110001","01101101","01101010","01100111", "01100100","01100001","01011110","01011011","01010111","01010100","01010001","01001110","01001011","01001000", "01000101","01000010","00111111","00111100","00111001","00110111","00110100","00110001","00101110","00101100", "00101001","00100111","00100100","00100010","00100000","00011101","00011011","00011001","00010111","00010101", "00010011","00010001","00010000","00001110","00001100","00001011","00001010","00001000","00000111","00000110", "00000101","00000100","00000011","00000010","00000010","00000001","00000001","00000000","00000000","00000000", "00000000","00000000","00000000","00000000","00000001","00000001","00000010","00000010","00000011","00000100", "00000101","00000110","00000111","00001000","00001010","00001011","00001100","00001110","00010000","00010001", "00010011","00010101","00010111","00011001","00011011","00011101","00100000","00100010","00100100","00100111", "00101001","00101100","00101110","00110001","00110100","00110111","00111001","00111100","00111111","01000010", "01000101","01001000","01001011","01001110","01010001","01010100","01010111","01011011","01011110","01100001" ); begin process (out_clk) begin if (out_clk' event and out_clk = '1') then if( data_index = 199 ) then data_index <= CONV_STD_LOGIC_VECTOR(0,8); else data_index <= data_index + '1'; end if; end if; tmp_line <= SIN_DATA(CONV_INTEGER ( data_index )); ADC_0 <= tmp_line(0) ; ADC_1 <= tmp_line(1) ; ADC_2 <= tmp_line(2) ; ADC_3 <= tmp_line(3) ; ADC_4 <= tmp_line(4) ; ADC_5 <= tmp_line(5) ; ADC_6 <= tmp_line(6) ; ADC_7 <= tmp_line(7) ; end process; set_dat : SETDATA port map( MODE => IN_MODE, CLK => IN_CLK, DATA => IN_DATA, Q0 => cmp_data(0), Q1 => cmp_data(1), Q2 => cmp_data(2), Q3 => cmp_data(3), Q4 => cmp_data(4), Q5 => cmp_data(5), Q6 => cmp_data(6), Q7 => cmp_data(7), Q8 => cmp_data(8), Q9 => cmp_data(9), Q10 => cmp_data(10), Q11 => cmp_data(11), Q12 => cmp_data(12), Q13 => cmp_data(13), Q14 => cmp_data(14), Q15 => cmp_data(15), Q16 => cmp_data(16), Q17 => cmp_data(17), Q18 => cmp_data(18), Q19 => cmp_data(19), Q20 => cmp_data(20), Q21 => cmp_data(21), Q22 => cmp_data(22), Q23 => cmp_data(23), Q24 => cmp_data(24)); cnt_prcs : COMPARE_HEX port map( IN_0 => cmp_data(0), IN_1 => cmp_data(1), IN_2 => cmp_data(2), IN_3 => cmp_data(3), IN_4 => cmp_data(4), IN_5 => cmp_data(5), IN_6 => cmp_data(6), IN_7 => cmp_data(7), IN_8 => cmp_data(8), IN_9 => cmp_data(9), IN_10 => cmp_data(10), IN_11 => cmp_data(11), IN_12 => cmp_data(12), IN_13 => cmp_data(13), IN_14 => cmp_data(14), IN_15 => cmp_data(15), IN_16 => cmp_data(16), IN_17 => cmp_data(17), IN_18 => cmp_data(18), IN_19 => cmp_data(19), IN_20 => cmp_data(20), IN_21 => cmp_data(21), IN_22 => cmp_data(22), IN_23 => cmp_data(23), IN_24 => cmp_data(24), CLK => SYS_CLK, OUT_CLK => out_clk); END rtl;