library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SETDATA is
    port(
        MODE : in  std_logic;
        CLK  : in  std_logic;    	
        DATA : in  std_logic;
        Q0   : out std_logic;
        Q1   : out std_logic;
        Q2   : out std_logic;
        Q3   : out std_logic;
        Q4   : out std_logic;
        Q5   : out std_logic;
        Q6   : out std_logic;
        Q7   : out std_logic;
        Q8   : out std_logic;
        Q9   : out std_logic;
        Q10  : out std_logic;
        Q11  : out std_logic;
        Q12  : out std_logic;
        Q13  : out std_logic;
        Q14  : out std_logic;
        Q15  : out std_logic;
        Q16  : out std_logic;
        Q17  : out std_logic;
        Q18  : out std_logic;
        Q19  : out std_logic;
        Q20  : out std_logic;
        Q21  : out std_logic;
        Q22  : out std_logic;
        Q23  : out std_logic;
        Q24  : out std_logic);
end SETDATA;

architecture rtl of SETDATA is
    signal counter : std_logic_vector(24 downto 0);
    signal tmp_cnt : std_logic_vector(24 downto 0);
begin
    process(CLK)
    begin
        if(CLK'event and CLK='1') then
            tmp_cnt <= tmp_cnt(23 downto 0) & DATA;    
        end if;	
    end process;
    
    process(MODE)
    begin
        if( MODE='1') then
            counter <= tmp_cnt; 
        end if;
    end process;
                   
    Q0  <= counter(0);
    Q1  <= counter(1);
    Q2  <= counter(2);
    Q3  <= counter(3);
    Q4  <= counter(4);
    Q5  <= counter(5);
    Q6  <= counter(6);
    Q7  <= counter(7);
    Q8  <= counter(8);
    Q9  <= counter(9);
    Q10 <= counter(10);
    Q11 <= counter(11);
    Q12 <= counter(12);
    Q13 <= counter(13);
    Q14 <= counter(14);
    Q15 <= counter(15);
    Q16 <= counter(16);
    Q17 <= counter(17);
    Q18 <= counter(18);
    Q19 <= counter(19);
    Q20 <= counter(20);
    Q21 <= counter(21);
    Q22 <= counter(22);
    Q23 <= counter(23);
    Q24 <= counter(24);

end rtl;