--******************************************************************************************
--  MAX3000A Sample Program
--   Project      :
--   Program Name :
--   Programer    :
--   Create date  :  Version 1.0    H24.12.02
--   History      :
--   Laungage     :  VHDL (ALTERA Quartus2 Version 8.1) 
--******************************************************************************************
--   Description
--
--******************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SAMPLE01 is
    Port ( LED_0 : out  STD_LOGIC;
           LED_1 : out  STD_LOGIC;
           LED_2 : out  STD_LOGIC;
           LED_3 : out  STD_LOGIC;
           LED_4 : out  STD_LOGIC;
           LED_5 : out  STD_LOGIC;
           LED_6 : out  STD_LOGIC;
           LED_7 : out  STD_LOGIC;
           IN_SW : in   STD_LOGIC);
end SAMPLE01;

ARCHITECTURE rtl of SAMPLE01 IS
  COMPONENT TESTCNT
  PORT(
    CLK : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic
  );
  END COMPONENT;
  COMPONENT TESTDEC
  PORT(
    IN_A  : IN std_logic;
    IN_B  : IN std_logic;
    IN_C  : IN std_logic;
    IN_D  : IN std_logic;
    LED_A : out std_logic;
    LED_B : out std_logic;
    LED_C : out std_logic;
    LED_D : out std_logic;
    LED_E : out std_logic;
    LED_F : out std_logic;
    LED_G : out std_logic;
    LED_H : out std_logic
  );
  END COMPONENT;

SIGNAL LA : std_logic;
SIGNAL LB : std_logic;
SIGNAL LC : std_logic;
SIGNAL LD : std_logic;

BEGIN

  cnt : TESTCNT port map(
    CLK => IN_SW,	 
    QA  => LA,
    QB  => LB,
    QC  => LC,
    QD  => LD
  );
  dec : TESTDEC port map(
    IN_A => LA,
    IN_B => LB,
    IN_C => LC,
    IN_D => LD,
    LED_A  => LED_0,
    LED_B  => LED_1,
    LED_C  => LED_2,
    LED_D  => LED_3,
    LED_E  => LED_4,
    LED_F  => LED_5,
    LED_G  => LED_6,    
    LED_H  => LED_7
	 
  );
END rtl;