library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TESTCNT IS
  PORT(
    CLK : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic
    );
END TESTCNT;

ARCHITECTURE rtl of TESTCNT IS
    SIGNAL counter : std_logic_vector(3 downto 0);
BEGIN
    PROCESS(CLK)
    BEGIN
        if(CLK'event and CLK='1') then
            if( counter = 7 ) then
                counter <= CONV_STD_LOGIC_VECTOR(0,4);
            else 
                counter <= counter + 1;
            end if;					 
        end if;
    END PROCESS;
    
    QA <= counter(0);
    QB <= counter(1);
    QC <= counter(2);
    QD <= counter(3);
end rtl;