--******************************************************************************************
--  MAX3000A Sample Program
--   Project      :
--   Program Name :
--   Programer    :
--   Create date  :  Version 1.0    H24.12.02
--   History      :
--   Laungage     :  VHDL (ALTERA Quartus2 Version 8.1) 
--******************************************************************************************
--   Description
--
--******************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SAMPLE01 is
    Port ( LED_0  : out  STD_LOGIC;
           LED_1  : out  STD_LOGIC;
           LED_2  : out  STD_LOGIC;
           LED_3  : out  STD_LOGIC;
           LED_4  : out  STD_LOGIC;
           LED_5  : out  STD_LOGIC;
           LED_6  : out  STD_LOGIC;
           LED_7  : out  STD_LOGIC;          
           IN_SW1 : in   STD_LOGIC;
           IN_SW2 : in   STD_LOGIC);
end SAMPLE01;

architecture Behavioral of SAMPLE01 is

begin
   LED_0 <= IN_SW1 ;
   LED_1 <= NOT IN_SW1 ;
   LED_2 <= IN_SW1 AND  IN_SW2 ;
   LED_3 <= IN_SW1 OR   IN_SW2 ;
   LED_4 <= IN_SW2 NAND IN_SW2 ;
   LED_5 <= IN_SW2 NOR  IN_SW2;
   LED_6 <= IN_SW1 XOR  IN_SW2 ;
   LED_7 <= IN_SW1 XNOR IN_SW2 ;
end Behavioral;