--******************************************************************************************
--  MAX3000A Sample Program
--   Project      :
--   Program Name :
--   Programer    :
--   Create date  :  Version 1.0    H24.12.18
--   History      :
--   Laungage     :  VHDL (ALTERA Quartus2 Version 8.1) 
--******************************************************************************************
--   Description
--
--******************************************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SAMPLE01 is
    Port ( 
        ADC_0  : out  STD_LOGIC;
        ADC_1  : out  STD_LOGIC;
        ADC_2  : out  STD_LOGIC;
        ADC_3  : out  STD_LOGIC;
        ADC_4  : out  STD_LOGIC;
        ADC_5  : out  STD_LOGIC;
        ADC_6  : out  STD_LOGIC;
        ADC_7  : out  STD_LOGIC;
        IN_CLK : in   STD_LOGIC);
end SAMPLE01;

architecture behavioral of SAMPLE01 is
        signal tmp_line   : std_logic_vector(7 downto 0);
	signal data_index : std_logic_vector(7 downto 0);
	subtype data_val is std_logic_vector(7 downto 0);
	type data_val_array is array (0 to 199) of data_val;
 	constant SIN_DATA : data_val_array := (
    "01100100","01100111","01101010","01101101","01110001","01110100","01110111","01111010","01111101","10000000",
    "10000011","10000110","10001001","10001100","10001111","10010001","10010100","10010111","10011010","10011100",
    "10011111","10100001","10100100","10100110","10101000","10101011","10101101","10101111","10110001","10110011",
    "10110101","10110111","10111000","10111010","10111100","10111101","10111110","11000000","11000001","11000010",
    "11000011","11000100","11000101","11000110","11000110","11000111","11000111","11001000","11001000","11001000",
    "11001000","11001000","11001000","11001000","11000111","11000111","11000110","11000110","11000101","11000100",
    "11000011","11000010","11000001","11000000","10111110","10111101","10111100","10111010","10111000","10110111",
    "10110101","10110011","10110001","10101111","10101101","10101011","10101000","10100110","10100100","10100001",
    "10011111","10011100","10011010","10010111","10010100","10010001","10001111","10001100","10001001","10000110",
    "10000011","10000000","01111101","01111010","01110111","01110100","01110001","01101101","01101010","01100111",
    "01100100","01100001","01011110","01011011","01010111","01010100","01010001","01001110","01001011","01001000",
    "01000101","01000010","00111111","00111100","00111001","00110111","00110100","00110001","00101110","00101100",
    "00101001","00100111","00100100","00100010","00100000","00011101","00011011","00011001","00010111","00010101",
    "00010011","00010001","00010000","00001110","00001100","00001011","00001010","00001000","00000111","00000110",
    "00000101","00000100","00000011","00000010","00000010","00000001","00000001","00000000","00000000","00000000",
    "00000000","00000000","00000000","00000000","00000001","00000001","00000010","00000010","00000011","00000100",
    "00000101","00000110","00000111","00001000","00001010","00001011","00001100","00001110","00010000","00010001",
    "00010011","00010101","00010111","00011001","00011011","00011101","00100000","00100010","00100100","00100111",
    "00101001","00101100","00101110","00110001","00110100","00110111","00111001","00111100","00111111","01000010",
    "01000101","01001000","01001011","01001110","01010001","01010100","01010111","01011011","01011110","01100001"    );

begin
    process (IN_CLK) begin
        if (IN_CLK' event and IN_CLK = '1') then
            if( data_index = 199 ) then
                data_index <= CONV_STD_LOGIC_VECTOR(0,8);
            else 
                data_index <= data_index + '1';
            end if;
        end if;

        tmp_line <= SIN_DATA(CONV_INTEGER ( data_index ));

        ADC_0 <= tmp_line(0) ;
        ADC_1 <= tmp_line(1) ;
        ADC_2 <= tmp_line(2) ;
        ADC_3 <= tmp_line(3) ;
        ADC_4 <= tmp_line(4) ;
        ADC_5 <= tmp_line(5) ;
        ADC_6 <= tmp_line(6) ;
        ADC_7 <= tmp_line(7) ;

    end process;
end behavioral;