--******************************************************************************************
--  MAX3000A Sample Program
--   Project      :
--   Program Name :
--   Programer    :
--   Create date  :  Version 1.0    H24.12.18
--   History      :
--   Laungage     :  VHDL (ALTERA Quartus2 Version 8.1) 
--******************************************************************************************
--   Description
--
--******************************************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY SAMPLE01 IS
  PORT(
    IN_MODE : in  std_logic;
    IN_CLK  : in  std_logic;
    IN_DATA : in  std_logic;
    LED_0   : out std_logic;
    LED_1   : out std_logic;
    LED_2   : out std_logic;
    LED_3   : out std_logic;
    LED_4   : out std_logic;
    LED_5   : out std_logic;
    LED_6   : out std_logic;   
    LED_7   : out std_logic
	 
  );
END SAMPLE01;

ARCHITECTURE rtl of SAMPLE01 IS
  COMPONENT SETDATA
  PORT(
    MODE: in  std_logic;
    CLK : in  std_logic;
    DATA: in  std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic;
    QE  : out std_logic;
    QF  : out std_logic;
    QG  : out std_logic;
    QH  : out std_logic
  );
  END COMPONENT;

BEGIN
  cnt : SETDATA port map(
    MODE=> IN_MODE,
    CLK => IN_CLK,	   
    DATA=> IN_DATA,	 
    QA  => LED_0,
    QB  => LED_1,
    QC  => LED_2,
    QD  => LED_3,
    QE  => LED_4,
    QF  => LED_5,
    QG  => LED_6,
    QH  => LED_7
  );  
END rtl;