library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SETDATA IS
  PORT(
    MODE: in  std_logic;
    CLK : in  std_logic;    	
    DATA: in  std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic;
    QE  : out std_logic;
    QF  : out std_logic;
    QG  : out std_logic;
    QH  : out std_logic
    );
END SETDATA;

ARCHITECTURE rtl of SETDATA IS
    SIGNAL counter : std_logic_vector(7 downto 0);
    SIGNAL tmp_cnt : std_logic_vector(7 downto 0);
BEGIN
    PROCESS(CLK)
    BEGIN
        if(CLK'event and CLK='1') then
            tmp_cnt <= tmp_cnt(6 downto 0) & DATA;    
        end if;	
    END PROCESS;
    
    PROCESS(MODE)
    BEGIN
        if( MODE='1') then
            counter <= tmp_cnt; 
        end if;
    END PROCESS;
                   
    QA <= counter(0);
    QB <= counter(1);
    QC <= counter(2);
    QD <= counter(3);
    QE <= counter(4);
    QF <= counter(5);
    QG <= counter(6);
    QH <= counter(7);
end rtl;