--****************************************************************************************** -- MAX3000A Sample Program -- Project : -- Program Name : -- Programer : -- Create date : Version 1.0 H24.12.02 -- History : -- Laungage : VHDL (ALTERA Quartus2 Version 8.1) --****************************************************************************************** -- Description -- --****************************************************************************************** library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SAMPLE01 IS PORT( LED_A : out STD_LOGIC; LED_B : out STD_LOGIC; LED_C : out STD_LOGIC; LED_D : out STD_LOGIC; LED_E : out STD_LOGIC; LED_F : out STD_LOGIC; LED_G : out STD_LOGIC; LED_DP : out STD_LOGIC; SEL_1 : out STD_LOGIC; SEL_2 : out STD_LOGIC; SEL_3 : out STD_LOGIC; SEL_4 : out STD_LOGIC; IN_SW1 : in STD_LOGIC; IN_SW2 : in STD_LOGIC; IN_OSC : in STD_LOGIC ); END SAMPLE01; ARCHITECTURE rtl of SAMPLE01 IS COMPONENT TEST7490 PORT( CLK : in std_logic; QA : out std_logic; QB : out std_logic; QC : out std_logic; QD : out std_logic; RST : in std_logic ); END COMPONENT; COMPONENT CRYCNT PORT( CLK : in std_logic; SBIT: in std_logic; Q : out std_logic ); END COMPONENT; COMPONENT TEST7447 PORT( IN_A : in std_logic; IN_B : in std_logic; IN_C : in std_logic; IN_D : in std_logic; LED_A : out std_logic; LED_B : out std_logic; LED_C : out std_logic; LED_D : out std_logic; LED_E : out std_logic; LED_F : out std_logic; LED_G : out std_logic ); END COMPONENT; COMPONENT TEST7493 PORT( CLK : in std_logic; QA : out std_logic; QB : out std_logic; QC : out std_logic; RST : in std_logic ); END COMPONENT; COMPONENT TESTDEC PORT( IN_A : in std_logic; IN_B : in std_logic; IN_C : in std_logic; DAT_A : out std_logic; DAT_B : out std_logic; DAT_C : out std_logic; DAT_D : out std_logic; DAT_E : out std_logic; DAT_F : out std_logic; DAT_G : out std_logic; DAT_H : out std_logic ); END COMPONENT; SIGNAL L1A : std_logic; SIGNAL L1B : std_logic; SIGNAL L1C : std_logic; SIGNAL L1D : std_logic; SIGNAL L2A : std_logic; SIGNAL L2B : std_logic; SIGNAL L2C : std_logic; SIGNAL L2D : std_logic; SIGNAL L3A : std_logic; SIGNAL L3B : std_logic; SIGNAL L3C : std_logic; SIGNAL L3D : std_logic; SIGNAL L4A : std_logic; SIGNAL L4B : std_logic; SIGNAL L4C : std_logic; SIGNAL L4D : std_logic; SIGNAL LED_1A : std_logic; SIGNAL LED_1B : std_logic; SIGNAL LED_1C : std_logic; SIGNAL LED_1D : std_logic; SIGNAL LED_1E : std_logic; SIGNAL LED_1F : std_logic; SIGNAL LED_1G : std_logic; SIGNAL LED_2A : std_logic; SIGNAL LED_2B : std_logic; SIGNAL LED_2C : std_logic; SIGNAL LED_2D : std_logic; SIGNAL LED_2E : std_logic; SIGNAL LED_2F : std_logic; SIGNAL LED_2G : std_logic; SIGNAL LED_3A : std_logic; SIGNAL LED_3B : std_logic; SIGNAL LED_3C : std_logic; SIGNAL LED_3D : std_logic; SIGNAL LED_3E : std_logic; SIGNAL LED_3F : std_logic; SIGNAL LED_3G : std_logic; SIGNAL LED_4A : std_logic; SIGNAL LED_4B : std_logic; SIGNAL LED_4C : std_logic; SIGNAL LED_4D : std_logic; SIGNAL LED_4E : std_logic; SIGNAL LED_4F : std_logic; SIGNAL LED_4G : std_logic; SIGNAL Q1 : std_logic; SIGNAL Q2 : std_logic; SIGNAL SEL_LQ0 : std_logic; SIGNAL SEL_LQ1 : std_logic; SIGNAL SEL_LQ2 : std_logic; SIGNAL SEL_LED1 : std_logic; SIGNAL SEL_LED2 : std_logic; SIGNAL SEL_LED3 : std_logic; SIGNAL SEL_LED4 : std_logic; SIGNAL DUM_LED1 : std_logic; SIGNAL DUM_LED2 : std_logic; SIGNAL DUM_LED3 : std_logic; SIGNAL DUM_LED4 : std_logic; BEGIN cry1 : CRYCNT port map( CLK => IN_OSC, SBIT => IN_SW1, Q => Q1 ); cnt1 : TEST7490 port map( CLK => Q1 , QA => L1A, QB => L1B, QC => L1C, QD => L1D, RST => IN_SW2 ); dec1 : TEST7447 port map( IN_A => L1A, IN_B => L1B, IN_C => L1C, IN_D => L1D, LED_A => LED_1A, LED_B => LED_1B, LED_C => LED_1C, LED_D => LED_1D, LED_E => LED_1E, LED_F => LED_1F, LED_G => LED_1G ); cnt2 : TEST7490 port map( CLK => L1D, QA => L2A, QB => L2B, QC => L2C, QD => L2D, RST => IN_SW2 ); dec2 : TEST7447 port map( IN_A => L2A, IN_B => L2B, IN_C => L2C, IN_D => L2D, LED_A => LED_2A, LED_B => LED_2B, LED_C => LED_2C, LED_D => LED_2D, LED_E => LED_2E, LED_F => LED_2F, LED_G => LED_2G ); cnt3 : TEST7490 port map( CLK => L2D, QA => L3A, QB => L3B, QC => L3C, QD => L3D, RST => IN_SW2 ); dec3 : TEST7447 port map( IN_A => L3A, IN_B => L3B, IN_C => L3C, IN_D => L3D, LED_A => LED_3A, LED_B => LED_3B, LED_C => LED_3C, LED_D => LED_3D, LED_E => LED_3E, LED_F => LED_3F, LED_G => LED_3G ); cnt4 : TEST7490 port map( CLK => L3D, QA => L4A, QB => L4B, QC => L4C, QD => L4D, RST => IN_SW2 ); dec4 : TEST7447 port map( IN_A => L4A, IN_B => L4B, IN_C => L4C, IN_D => L4D, LED_A => LED_4A, LED_B => LED_4B, LED_C => LED_4C, LED_D => LED_4D, LED_E => LED_4E, LED_F => LED_4F, LED_G => LED_4G ); selledcnt : TEST7493 port map( CLK => IN_OSC, QA => SEL_LQ0, QB => SEL_LQ1, QC => SEL_LQ2, RST => IN_SW2 ); selled : TESTDEC port map( IN_A => SEL_LQ0, IN_B => SEL_LQ1, IN_C => SEL_LQ2, DAT_A => DUM_LED1, DAT_B => SEL_LED1, DAT_C => DUM_LED2, DAT_D => SEL_LED2, DAT_E => DUM_LED3, DAT_F => SEL_LED3, DAT_G => DUM_LED4, DAT_H => SEL_LED4 ); SEL_1 <= SEL_LED1; SEL_2 <= SEL_LED2; SEL_3 <= SEL_LED3; SEL_4 <= SEL_LED4; LED_DP<= '1'; LED_A <= ( SEL_LED1 AND LED_1A ) OR ( SEL_LED2 AND LED_2A ) OR ( SEL_LED3 AND LED_3A ) OR ( SEL_LED4 AND LED_4A ); LED_B <= ( SEL_LED1 AND LED_1B ) OR ( SEL_LED2 AND LED_2B ) OR ( SEL_LED3 AND LED_3B ) OR ( SEL_LED4 AND LED_4B ); LED_C <= ( SEL_LED1 AND LED_1C ) OR ( SEL_LED2 AND LED_2C ) OR ( SEL_LED3 AND LED_3C ) OR ( SEL_LED4 AND LED_4C ); LED_D <= ( SEL_LED1 AND LED_1D ) OR ( SEL_LED2 AND LED_2D ) OR ( SEL_LED3 AND LED_3D ) OR ( SEL_LED4 AND LED_4D ); LED_E <= ( SEL_LED1 AND LED_1E ) OR ( SEL_LED2 AND LED_2E ) OR ( SEL_LED3 AND LED_3E ) OR ( SEL_LED4 AND LED_4E ); LED_F <= ( SEL_LED1 AND LED_1F ) OR ( SEL_LED2 AND LED_2F ) OR ( SEL_LED3 AND LED_3F ) OR ( SEL_LED4 AND LED_4F ); LED_G <= ( SEL_LED1 AND LED_1G ) OR ( SEL_LED2 AND LED_2G ) OR ( SEL_LED3 AND LED_3G ) OR ( SEL_LED4 AND LED_4G ); END rtl;