--******************************************************************************************
--  MAX3000A Sample Program
--   Project      :
--   Program Name :
--   Programer    :
--   Create date  :  Version 1.0    H24.12.02
--   History      :
--   Laungage     :  VHDL (ALTERA Quartus2 Version 8.1) 
--******************************************************************************************
--   Description
--
--******************************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY TEST7493 IS
    PORT(
        CLK : IN std_logic;
        QA  : out std_logic;
        QB  : out std_logic;
        QC  : out std_logic;
        RST : IN std_logic
    );
END TEST7493;

ARCHITECTURE rtl of TEST7493 IS
    SIGNAL counter : std_logic_vector(2 downto 0);
BEGIN

    PROCESS(CLK)
        BEGIN
--          if(CLK'event and CLK='1') then
            if(CLK'event and CLK='0') then
                counter <= counter + 1;
            end if;
	        if(RST='1') then
                counter <= CONV_STD_LOGIC_VECTOR(0,3);
	        end if;
    END PROCESS;

    QA <= counter(0);
    QB <= counter(1);
    QC <= counter(2);
end rtl;