--******************************************************************************************
--  MAX3000A Sample Program
--   Project      :
--   Program Name :
--   Programer    :
--   Create date  :  Version 1.0    H24.12.02
--   History      :
--   Laungage     :  VHDL (ALTERA Quartus2 Version 8.1) 
--******************************************************************************************
--   Description
--
--******************************************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TESTDEC IS
    PORT( 
        IN_A  : IN std_logic;
        IN_B  : IN std_logic;
        IN_C  : IN std_logic;
        DAT_A : out std_logic;
        DAT_B : out std_logic;
        DAT_C : out std_logic;
        DAT_D : out std_logic;
        DAT_E : out std_logic;
        DAT_F : out std_logic;    
        DAT_G : out std_logic;	 
        DAT_H : out std_logic
    );
END TESTDEC;

ARCHITECTURE rtl of TESTDEC IS  
    SIGNAL number    : std_logic_vector(2 downto 0);  
BEGIN
    number(0) <= IN_A;
    number(1) <= IN_B;
    number(2) <= IN_C;
  
    DAT_A <= '1' when number = 0 else
             '0';
    DAT_B <= '1' when number = 1 else
             '0';
    DAT_C <= '1' when number = 2 else
             '0';
    DAT_D <= '1' when number = 3 else
             '0';
    DAT_E <= '1' when number = 4 else
             '0';
    DAT_F <= '1' when number = 5 else
             '0';
    DAT_G <= '1' when number = 6 else
             '0'; 
    DAT_H <= '1' when number = 7 else
             '0'; 				  
end rtl;