--******************************************************************************************
--  MAX3000A Sample Program
--   Project      :
--   Program Name :
--   Programer    :
--   Create date  :  Version 1.0    H24.12.02
--   History      :
--   Laungage     :  VHDL (ALTERA Quartus2 Version 8.1) 
--******************************************************************************************
--   Description
--
--******************************************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


ENTITY CRYCNT IS
    PORT(
    CLK  : IN std_logic;
    SBIT : IN std_logic;
    Q    : out std_logic
    );
END CRYCNT;

ARCHITECTURE rtl of CRYCNT IS
    SIGNAL counter : std_logic_vector(9 downto 0);
BEGIN

    PROCESS(CLK)
    BEGIN
--      if(CLK'event and CLK='1') then
        if((CLK'event and CLK='0' ) and SBIT = '1' ) then
--          if( counter = 999 ) then
            if( counter = 9   ) then
                counter <= CONV_STD_LOGIC_VECTOR(0,10);
            else
                counter <= counter + 1;
            end if;
        end if;
    END PROCESS;
  
--  Q <= counter(9);
    Q <= counter(3);
end rtl;