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-- Company: 
-- Engineer: 
-- 
-- Create Date:    05:13:04 08/07/2006 
-- Design Name: 
-- Module Name:    TEST0001 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TEST0001 is
    Port ( LED_A : out  STD_LOGIC;
           LED_B : out  STD_LOGIC;
           LED_C : out  STD_LOGIC;
           LED_D : out  STD_LOGIC;
           LED_E : out  STD_LOGIC;
           LED_F : out  STD_LOGIC;
           LED_G : out  STD_LOGIC;
           LED_H : out  STD_LOGIC;
           IN_SW : in  STD_LOGIC);
end TEST0001;

architecture Behavioral of TEST0001 is

begin
   LED_A <= IN_SW ;
   LED_B <= IN_SW ;
	LED_C <= IN_SW ;
   LED_D <= IN_SW ;
   LED_E <= IN_SW ;
   LED_F <= IN_SW ;
	LED_G <= IN_SW ;
   LED_H <= IN_SW ;
end Behavioral;