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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:02:49 08/07/2006 
-- Design Name: 
-- Module Name:    test03 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY TEST7442 IS
  PORT( 
    IN_A  : IN std_logic;
    IN_B  : IN std_logic;
    IN_C  : IN std_logic;
    IN_D  : IN std_logic;
    LED_A : out std_logic;
    LED_B : out std_logic;
    LED_C : out std_logic;
    LED_D : out std_logic;
    LED_E : out std_logic;
    LED_F : out std_logic;    
	 LED_G : out std_logic;	 
    LED_H : out std_logic
    );
END TEST7442;

ARCHITECTURE rtl of TEST7442 IS
  SIGNAL number : std_logic_vector(3 downto 0);
BEGIN
  number(0) <= IN_A;
  number(1) <= IN_B;
  number(2) <= IN_C;
  number(3) <= IN_D;
  LED_A <= '1' when number = 0 else
           '0';
  LED_B <= '1' when number = 1 else
           '0';
  LED_C <= '1' when number = 2 else
           '0';
  LED_D <= '1' when number = 3 else
           '0';
  LED_E <= '1' when number = 4 else
           '0';
  LED_F <= '1' when number = 5 else
           '0';
  LED_G <= '1' when number = 6 else
           '0'; 
  LED_H <= '1' when number = 7 else
           '0'; 	
			  
end rtl;