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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:58:02 08/07/2006 
-- Design Name: 
-- Module Name:    test01 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY test0002 IS
  PORT(
           LED_1A : out  STD_LOGIC;
           LED_1B : out  STD_LOGIC;
           LED_1C : out  STD_LOGIC;
			  LED_1D : out  STD_LOGIC;
           LED_1E : out  STD_LOGIC;
           LED_1F : out  STD_LOGIC;
			  LED_1G : out  STD_LOGIC;
			  LED_2A : out  STD_LOGIC;
           LED_2B : out  STD_LOGIC;
           LED_2C : out  STD_LOGIC;
			  LED_2D : out  STD_LOGIC;
           LED_2E : out  STD_LOGIC;
           LED_2F : out  STD_LOGIC;
			  LED_2G : out  STD_LOGIC;
		     LED_3A : out  STD_LOGIC;
           LED_3B : out  STD_LOGIC;
           LED_3C : out  STD_LOGIC;
			  LED_3D : out  STD_LOGIC;
           LED_3E : out  STD_LOGIC;
           LED_3F : out  STD_LOGIC;
			  LED_3G : out  STD_LOGIC;
			  LED_4A : out  STD_LOGIC;
           LED_4B : out  STD_LOGIC;
           LED_4C : out  STD_LOGIC;
			  LED_4D : out  STD_LOGIC;
           LED_4E : out  STD_LOGIC;
           LED_4F : out  STD_LOGIC;
			  LED_4G : out  STD_LOGIC;
           IN_SW1 : in  STD_LOGIC;
           IN_SW2 : in  STD_LOGIC;
           IN_OSC : in  STD_LOGIC	
  );
END test0002;

ARCHITECTURE rtl of test0002 IS
  COMPONENT TEST7490
  PORT(
    CLK : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic;
	 RST : IN std_logic
  );
  END COMPONENT;
  
  COMPONENT TEST7490UP
  PORT(
    CLK : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic;
 	 RST : IN std_logic
  );
  END COMPONENT;
  
  COMPONENT CRYCNT
  PORT(
    CLK : IN std_logic;
	 SBIT : IN std_logic;
    Q   : out std_logic
  );
  END COMPONENT;
  
  COMPONENT TEST7447
  PORT(
    IN_A  : IN std_logic;
    IN_B  : IN std_logic;
    IN_C  : IN std_logic;
    IN_D  : IN std_logic;
    LED_A : out std_logic;
    LED_B : out std_logic;
    LED_C : out std_logic;
    LED_D : out std_logic;
    LED_E : out std_logic;
    LED_F : out std_logic;
    LED_G : out std_logic
  );
  END COMPONENT;
SIGNAL L1A : std_logic;
SIGNAL L1B : std_logic;
SIGNAL L1C : std_logic;
SIGNAL L1D : std_logic;

SIGNAL L2A : std_logic;
SIGNAL L2B : std_logic;
SIGNAL L2C : std_logic;
SIGNAL L2D : std_logic;

SIGNAL L3A : std_logic;
SIGNAL L3B : std_logic;
SIGNAL L3C : std_logic;
SIGNAL L3D : std_logic;

SIGNAL L4A : std_logic;
SIGNAL L4B : std_logic;
SIGNAL L4C : std_logic;
SIGNAL L4D : std_logic;

SIGNAL Q1 : std_logic;

BEGIN

  cry1 : CRYCNT port map(
    CLK => IN_OSC,
	 SBIT => IN_SW1,
    Q  => Q1
  );
  
  cnt1 : TEST7490 port map(
    CLK => Q1 ,
    QA  => L1A,
    QB  => L1B,
    QC  => L1C,
    QD  => L1D,
	 RST => IN_SW2
  );
  
  dec1 : TEST7447 port map(
    IN_A => L1A,
    IN_B => L1B,
    IN_C => L1C,
    IN_D => L1D,
    LED_A  => LED_1A,
    LED_B  => LED_1B,
    LED_C  => LED_1C,
    LED_D  => LED_1D,
    LED_E  => LED_1E,
    LED_F  => LED_1F,
    LED_G  => LED_1G	 
  );
  
   cnt2 : TEST7490 port map(
    CLK => L1D,
    QA  => L2A,
    QB  => L2B,
    QC  => L2C,
    QD  => L2D,
	 RST => IN_SW2
  );
  dec2 : TEST7447 port map(
    IN_A => L2A,
    IN_B => L2B,
    IN_C => L2C,
    IN_D => L2D,
    LED_A  => LED_2A,
    LED_B  => LED_2B,
    LED_C  => LED_2C,
    LED_D  => LED_2D,
    LED_E  => LED_2E,
    LED_F  => LED_2F,
    LED_G  => LED_2G	 
  );
  
  cnt3 : TEST7490 port map(
    CLK => L2D,
    QA  => L3A,
    QB  => L3B,
    QC  => L3C,
    QD  => L3D,
	 RST => IN_SW2
  );
  dec3 : TEST7447 port map(
    IN_A => L3A,
    IN_B => L3B,
    IN_C => L3C,
    IN_D => L3D,
    LED_A  => LED_3A,
    LED_B  => LED_3B,
    LED_C  => LED_3C,
    LED_D  => LED_3D,
    LED_E  => LED_3E,
    LED_F  => LED_3F,
    LED_G  => LED_3G	 
  );
  
   cnt4 : TEST7490 port map(
    CLK => L3D,
    QA  => L4A,
    QB  => L4B,
    QC  => L4C,
    QD  => L4D,
	 RST => IN_SW2
  );
  dec4 : TEST7447 port map(
    IN_A => L4A,
    IN_B => L4B,
    IN_C => L4C,
    IN_D => L4D,
    LED_A  => LED_4A,
    LED_B  => LED_4B,
    LED_C  => LED_4C,
    LED_D  => LED_4D,
    LED_E  => LED_4E,
    LED_F  => LED_4F,
    LED_G  => LED_4G	 
  );
  
END rtl;