----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:01:36 08/07/2006 
-- Design Name: 
-- Module Name:    test02 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY TEST7490 IS
  PORT(
    CLK : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic;
	 RST : IN std_logic
    );
END TEST7490;

ARCHITECTURE rtl of TEST7490 IS
  SIGNAL counter : std_logic_vector(3 downto 0);
BEGIN

  PROCESS(CLK)
  BEGIN
--    if(CLK'event and CLK='1') then
    if(CLK'event and CLK='0') then
      if( counter = 9 ) then
        counter <= CONV_STD_LOGIC_VECTOR(0,4);
      else
        counter <= counter + 1;
      end if;
    end if;
	 if(RST='1') then
        counter <= CONV_STD_LOGIC_VECTOR(0,4);
	 end if;
  END PROCESS;

  QA <= counter(0);
  QB <= counter(1);
  QC <= counter(2);
  QD <= counter(3);
end rtl;