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-- Company: 
-- Engineer: 
-- 
-- Create Date:    22:57:02 03/27/2012 
-- Design Name: 
-- Module Name:    PRG01 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TEST0001 is
    Port ( LED_0 : out  STD_LOGIC;
           LED_1 : out  STD_LOGIC;
           LED_2 : out  STD_LOGIC;
           LED_3 : out  STD_LOGIC;
           LED_4 : out  STD_LOGIC;
           LED_5 : out  STD_LOGIC;
           LED_6 : out  STD_LOGIC;
           LED_7 : out  STD_LOGIC;
           IN_SW : in   STD_LOGIC);
end TEST0001;

architecture Behavioral of TEST0001 is

begin
   LED_0 <= IN_SW ;
   LED_1 <= IN_SW ;
   LED_2 <= IN_SW ;
   LED_3 <= IN_SW ;
   LED_4 <= IN_SW ;
   LED_5 <= IN_SW ;
   LED_6 <= IN_SW ;
   LED_7 <= IN_SW ;
end Behavioral;