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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:04:24 03/28/2012 
-- Design Name: 
-- Module Name:    PRG01 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY test0001 IS
  PORT(
    IN_SW   : IN std_logic;
    LED1_0  : out std_logic;
    LED1_1  : out std_logic;
    LED1_2  : out std_logic;
    LED1_3  : out std_logic;
    LED1_4  : out std_logic;
    LED1_5  : out std_logic;
    LED1_6  : out std_logic;   
    LED1_7  : out std_logic
	 
  );
END test0001;

ARCHITECTURE rtl of test0001 IS
  COMPONENT TEST7493
  PORT(
    CLK : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic
  );
  END COMPONENT;
  COMPONENT TEST7442
  PORT(
    IN_A  : IN std_logic;
    IN_B  : IN std_logic;
    IN_C  : IN std_logic;
    IN_D  : IN std_logic;
    LED_A : out std_logic;
    LED_B : out std_logic;
    LED_C : out std_logic;
    LED_D : out std_logic;
    LED_E : out std_logic;
    LED_F : out std_logic;
    LED_G : out std_logic;
    LED_H : out std_logic
  );
  END COMPONENT;
SIGNAL LA : std_logic;
SIGNAL LB : std_logic;
SIGNAL LC : std_logic;
SIGNAL LD : std_logic;

BEGIN

  cnt : TEST7493 port map(
    CLK => IN_SW,
    QA  => LA,
    QB  => LB,
    QC  => LC,
    QD  => LD
  );
  dec : TEST7442 port map(
    IN_A => LA,
    IN_B => LB,
    IN_C => LC,
    IN_D => LD,
    LED_A  => LED1_0,
    LED_B  => LED1_1,
    LED_C  => LED1_2,
    LED_D  => LED1_3,
    LED_E  => LED1_4,
    LED_F  => LED1_5,
    LED_G  => LED1_6,    
    LED_H  => LED1_7
	 
  );
END rtl;