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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:39:15 03/28/2012 
-- Design Name: 
-- Module Name:    PRG03 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY TEST7442 IS
  PORT( 
    IN_A  : IN std_logic;
    IN_B  : IN std_logic;
    IN_C  : IN std_logic;
    IN_D  : IN std_logic;
    LED_A : out std_logic;
    LED_B : out std_logic;
    LED_C : out std_logic;
    LED_D : out std_logic;
    LED_E : out std_logic;
    LED_F : out std_logic;    
    LED_G : out std_logic;	 
    LED_H : out std_logic
    );
END TEST7442;

ARCHITECTURE rtl of TEST7442 IS  
  SIGNAL number    : std_logic_vector(3 downto 0);  
  SIGNAL tmp_data  : std_logic_vector(7 downto 0);
  
  SUBTYPE put1_data is std_logic_vector(7 downto 0);  
  TYPE rom_data is array (0 to 15) of put1_data;
  CONSTANT put1 : rom_data := (
      "00000001","00000011","00000111","00001111",
      "00011111","00111111","01111111","11111111",
      "01111111","00111111","00011111","00001111",
      "00000111","00000011","00000001","00000000"
  );

BEGIN
  number(0) <= IN_A;
  number(1) <= IN_B;
  number(2) <= IN_C;
  number(3) <= IN_D;

  tmp_data <= put1(conv_integer(number));
  
  LED_A <= tmp_data(0);
  LED_B <= tmp_data(1);
  LED_C <= tmp_data(2);
  LED_D <= tmp_data(3);
  LED_E <= tmp_data(4);
  LED_F <= tmp_data(5);
  LED_G <= tmp_data(6);
  LED_H <= tmp_data(7);
  
			  
end rtl;