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-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:08:57 03/30/2012 
-- Design Name: 
-- Module Name:    PROG02 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY TESTCNT IS
  PORT(
    CLK : IN std_logic;
    MODE: IN std_logic;	
    RST : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic
    );
END TESTCNT;

ARCHITECTURE rtl of TESTCNT IS
    SIGNAL counter : std_logic_vector(3 downto 0);
    SIGNAL tmp_cnt : std_logic_vector(3 downto 0);
BEGIN
    PROCESS(CLK,RST)
    BEGIN
        if(CLK'event and CLK='1') then
            if( tmp_cnt = 7 ) then
                tmp_cnt <= CONV_STD_LOGIC_VECTOR(0,4);
            else 
                tmp_cnt <= tmp_cnt + 1;
            end if;					 
        end if;
        if(RST='1') then
            tmp_cnt <= CONV_STD_LOGIC_VECTOR(0,4);
        end if;
    END PROCESS;
    
    PROCESS(MODE)
        BEGIN
            if( MODE='1') then
                counter <= tmp_cnt; 
            end if;
    END PROCESS;

    QA <= counter(0);
    QB <= counter(1);
    QC <= counter(2);
    QD <= counter(3);
end rtl;