----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:32:44 04/03/2012 
-- Design Name: 
-- Module Name:    PROG01 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY TEST0014 IS
  PORT(
      LED_1  : out  STD_LOGIC;
      LED_2  : out  STD_LOGIC;
      LED_3  : out  STD_LOGIC;
      LED_4  : out  STD_LOGIC;
      LED_5  : out  STD_LOGIC;
      LED_6  : out  STD_LOGIC;
      LED_7  : out  STD_LOGIC;
      SW_1   : in   STD_LOGIC;
      OSC    : in   STD_LOGIC	
  );
END TEST0014;

ARCHITECTURE rtl of TEST0014 IS
  COMPONENT COUNTER
  PORT(
    CLK : IN std_logic;
    SW  : IN std_logic;	 
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic
  );
  END COMPONENT;
    
  COMPONENT DECODER
  PORT(
    IN_A  : IN std_logic;
    IN_B  : IN std_logic;
    IN_C  : IN std_logic;
    IN_D  : IN std_logic;
    LED_A : out std_logic;
    LED_B : out std_logic;
    LED_C : out std_logic;
    LED_D : out std_logic;
    LED_E : out std_logic;
    LED_F : out std_logic;
    LED_G : out std_logic
  );
  END COMPONENT;
  
SIGNAL LN_A : std_logic;
SIGNAL LN_B : std_logic;
SIGNAL LN_C : std_logic;
SIGNAL LN_D : std_logic;

BEGIN
  
  cnt : COUNTER port map(
    CLK => OSC ,    
    SW  => SW_1,	 
    QA  => LN_A,
    QB  => LN_B,
    QC  => LN_C,
    QD  => LN_D
  );
  
  dec : DECODER port map(
    IN_A   => LN_A,
    IN_B   => LN_B,
    IN_C   => LN_C,
    IN_D   => LN_D,
    LED_A  => LED_1,
    LED_B  => LED_2,
    LED_C  => LED_3,
    LED_D  => LED_4,
    LED_E  => LED_5,
    LED_F  => LED_6,
    LED_G  => LED_7	 
  ); 
  
END rtl;