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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:37:00 04/03/2012 
-- Design Name: 
-- Module Name:    PROG02 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY COUNTER IS
  PORT(
    CLK : IN std_logic;
    SW  : IN std_logic;
    QA  : out std_logic;
    QB  : out std_logic;
    QC  : out std_logic;
    QD  : out std_logic
    );
END COUNTER;

ARCHITECTURE rtl of COUNTER IS
  SIGNAL counter : std_logic_vector(3 downto 0);
BEGIN

  PROCESS(CLK,SW)
  BEGIN
    if(CLK'event and CLK='1') then
--  if(CLK'event and CLK='0') then
      if( SW = '0' ) then
          if( counter = 5 ) then
              counter <= CONV_STD_LOGIC_VECTOR(0,4);
          else
              counter <= counter + 1;
          end if;
      end if;		
    end if;
  END PROCESS;

  QA <= counter(0);
  QB <= counter(1);
  QC <= counter(2);
  QD <= counter(3);
end rtl;