;****************************************************************************************** ; PIC12F1822 Sample Program ; Project : ; Program Name : ; Programer : ; Create date : Version 1.0 H27.04.01 ; History : ; Laungage : MPLAB MPASM ;****************************************************************************************** ; (1)Description ; OSC : Internal OSC 16MHz ; Assign I/O ; MSSP SCL:PORTA(1), SDA:PORTA(2) ; Caution:I2C pins pull-up is required by an external resistor ;****************************************************************************************** LIST P=PIC12F1822,ST=OFF,R=DEC INCLUDE "P12F1822.inc" __CONFIG _CONFIG1 , _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF __CONFIG _CONFIG2 , _WRT_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_HI & _LVP_OFF ; ; Define GENERAL PURPOSE RAM AREA (80 bytes maximum) ; TMP_WK EQU 20H ; ; Define Common RAM AREA (16 bytes) ; TMP_C EQU 70H I2C_DAT EQU 71H LCD_CMD EQU 72H ; Define Macro SELBANK MACRO #BANK_NO MOVLW #BANK_NO MOVWF BSR ENDM WAT001 MACRO #C_TMP MOVLW #C_TMP CALL WAIT_001S ENDM PUTCMD MACRO #C_TMP MOVLW #C_TMP MOVWF LCD_CMD CALL PUT_LCD_CMD ENDM PUTDAT MACRO #C_TMP MOVLW #C_TMP MOVWF LCD_CMD CALL PUT_LCD_DAT ENDM WAT1S MACRO WAT001 250 WAT001 250 WAT001 250 WAT001 250 ENDM ORG 0h GOTO START ORG 4h GOTO START START ; ***************************** ; 1.Initialize ; ***************************** ; (1)Define OSC (16MHz, IntOSC) SELBANK 1 MOVLW B'11111010' ; 16MHz MOVWF OSCCON ; (2)Define I/O port SELBANK 1 MOVLW B'11111111' MOVWF TRISA ; (3)Define APFCON Register ; SELBANK 2 ; BSF APFCON,RXDTSEL ; RX ==> RA5 ; BSF APFCON,TXCKSEL ; TX ==> RA4 ; (4)Initialized EUART ; CALL INTUART ; (5)Initialized INTMSSP CALL INTMSSP ; (6)Initialized LCD CALL INIT_LCD SELBANK 0 ; ***************************** ; 2.Program main ; ***************************** ; (1)Main loop MAIN CALL LCDDEMO1 GOTO MAIN ;****************************************************************************************** ; Program : LCDDEMO1 ; Title : ; Input : ; Output : ;****************************************************************************************** LCDDEMO1 ; ===================================== ; 1.Demo 01 ; ===================================== CALL SET_LCD1 PUTDAT 'P' PUTDAT 'I' PUTDAT 'C' PUTDAT '1' PUTDAT '2' PUTDAT 'F' PUTDAT '1' PUTDAT '8' PUTDAT '2' PUTDAT '2' PUTDAT ' ' PUTDAT 'O' PUTDAT 'K' PUTDAT ' ' PUTDAT '>' PUTDAT ' ' CALL SET_LCD2 PUTDAT 'S' PUTDAT 'O' PUTDAT '1' PUTDAT '6' PUTDAT '0' PUTDAT '2' PUTDAT 'A' PUTDAT 'W' PUTDAT ' ' PUTDAT 'I' PUTDAT '2' PUTDAT 'C' PUTDAT ' ' PUTDAT ' ' PUTDAT ' ' PUTDAT ' ' WAT1S ; ===================================== ; 2.Demo 02 ; ===================================== CALL SET_LCD1 PUTDAT '0' PUTDAT '1' PUTDAT '2' PUTDAT '3' PUTDAT '4' PUTDAT '5' PUTDAT '6' PUTDAT '7' PUTDAT '8' PUTDAT '9' PUTDAT 'A' PUTDAT 'B' PUTDAT 'C' PUTDAT 'D' PUTDAT 'E' PUTDAT 'F' CALL SET_LCD2 PUTDAT 'G' PUTDAT 'H' PUTDAT 'I' PUTDAT 'J' PUTDAT 'K' PUTDAT 'L' PUTDAT 'M' PUTDAT 'N' PUTDAT 'O' PUTDAT 'P' PUTDAT 'Q' PUTDAT 'R' PUTDAT 'S' PUTDAT 'T' PUTDAT 'U' PUTDAT 'V' WAT1S RETURN ;****************************************************************************************** ; Program : INIT_LCD ; Title : ; Input : ; Output : ; Description : From Akizuki electronic documentation ;****************************************************************************************** INIT_LCD WAT001 100 PUTCMD H'01' WAT001 20 PUTCMD H'02' WAT001 2 PUTCMD H'0F' WAT001 2 PUTCMD H'01' WAT001 20 PUTCMD H'2A' PUTCMD H'79' PUTCMD H'81' PUTCMD H'FF' PUTCMD H'78' PUTCMD H'28' WAT001 100 RETURN ;****************************************************************************************** ; Program : CLR_LCD ; Title : Clear Display ; Input : ; Output : ; Description : ;****************************************************************************************** CLR_LCD WAT001 2 PUTCMD H'01' WAT001 20 RETURN ;****************************************************************************************** ; Program : SET_LCD1 ; Title : Set the first line ; Input : ; Output : ; Description : ;****************************************************************************************** SET_LCD1 WAT001 2 PUTCMD H'80' WAT001 20 RETURN ;****************************************************************************************** ; Program : SET_LCD2 ; Title : Set the Second line ; Input : ; Output : ; Description : ;****************************************************************************************** SET_LCD2 WAT001 2 PUTCMD H'A0' ; 0x20 + 0x80 WAT001 20 RETURN ;****************************************************************************************** ; Program : PUT_LCD_CMD ; Title : ; Input : ; Output : ; Description : ;****************************************************************************************** PUT_LCD_CMD ; ***************************** ; 1.Issue the start condition and trancemission address ; ***************************** MOVLW H'78' MOVWF I2C_DAT CALL PUTI2CSTR ; ***************************** ; 2.Put LCD command ; ***************************** MOVLW H'00' MOVWF I2C_DAT CALL PUTI2CDAT MOVFW LCD_CMD MOVWF I2C_DAT CALL PUTI2CDAT ; ***************************** ; 3.Issue the stop condition ; ***************************** CALL PUTI2CSTP WAT001 10 RETURN ;****************************************************************************************** ; Program : PUT_LCD_DAT ; Title : ; Input : ; Output : ; Description : ;****************************************************************************************** PUT_LCD_DAT ; ***************************** ; 1.Issue the start condition and trancemission address ; ***************************** MOVLW H'78' MOVWF I2C_DAT CALL PUTI2CSTR ; ***************************** ; 2.Put LCD data ; ***************************** MOVLW H'40' MOVWF I2C_DAT CALL PUTI2CDAT MOVFW LCD_CMD MOVWF I2C_DAT CALL PUTI2CDAT ; ***************************** ; 3.Issue the stop condition ; ***************************** CALL PUTI2CSTP WAT001 1 RETURN ;****************************************************************************************** ; Program : INTMSSP ; Title : Initialized MSSP ; Input : ; Output : ; Description : ;****************************************************************************************** INTMSSP ; ******************************************************* ; 1.Define SSP1STAT(SSP1 STATUS REGISTER) (BANK4) ; SSP1STAT[7] SMP: SPI Data Input Sample bit ; SPI Master mode: ; 1 = Input data sampled at end of data output time / 0 = Input data sampled at middle of data output time ; SPI Slave mode: ; SMP must be cleared when SPI is used in Slave mode ; In I2 C Master or Slave mode: ; 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) ; 0 = Slew rate control enabled for high speed mode (400 kHz) ; SSP1STAT[6] CKE: SPI Clock Edge Select bit (SPI mode only) ; In SPI Master or Slave mode: ; 1 = Transmit occurs on transition from active to Idle clock state / 0 = Transmit occurs on transition from Idle to active clock state ; In I2C mode only: ; 1 = Enable input logic so that thresholds are compliant with SMBus specification ; 0 = Disable SMBus specific inputs ; SSP1STAT[5] D/A: Data/Address bit (I2C mode only) ; 1 = Indicates that the last byte received or transmitted was data ; 0 = Indicates that the last byte received or transmitted was address ; SSP1STAT[4] P: Stop bit (I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.) ; 1 = Indicates that a Stop bit has been detected last (this bit is e0f on Reset) ; 0 = Stop bit was not detected last ; SSP1STAT[3] S: Start bit(I2C mode only. This bit is cleared when the MSSP1 module is disabled, SSP1EN is cleared.) ; 1 = Indicates that a Start bit has been detected last (this bit is e0f on Reset) ; 0 = Start bit was not detected last ; SSP1STAT[2] R/W: Read/Write bit information (I2C mode only) ; This bit holds the R/W bit information following the last address match. ; This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. ; In I2 C Slave mode: 1 = Read / 0 = Write ; In I2 C Master mode: ; 1 = Transmit is in progress ; 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ; ACKEN will indicate if the MSSP1 is in Idle mode. ; SSP1STAT[1] UA: Update Address bit (10-bit I2C mode only) ; 1 = Indicates that the user needs to update the address in the SSP1ADD register ; 0 = Address does not need to be updated ; SSP1STAT[0] BF: Buffer Full Status bit ; Receive (SPI and I2 C modes): ; 1 = Receive complete, SSP1BUF is full ; 0 = Receive not complete, SSP1BUF is empty ; Transmit (I2 C mode only): ; 1 = Data transmit in progress (does not include the ACK and Stop bits), SSP1BUF is full ; 0 = Data transmit complete (does not include the ACK and Stop bits), SSP1BUF is empty ; ******************************************************* SELBANK 4 MOVLW B'10000000' MOVWF SSP1STAT ; ******************************************************* ; 2.Define SSP1CON1: SSP1 CONTROL REGISTER 1 (BANK4) ; SSP1CON1[7] WCOL: Write Collision Detect bit ; Master mode: ; 1 = A write to the SSP1BUF register was attempted while the I2C conditions were not valid for a transmission to be started ; 0 = No collision ; Slave mode: ; 1 = The SSP1BUF register is written while it is still transmitting the previous word (must be cleared in software) ; 0 = No collision ; SSP1CON1[6] SSP1OV: Receive Overflow Indicator bit(1) ; In SPI mode: ; 1 = A new byte is received while the SSP1BUF register is still holding the previous data. ; In case of overflow, the data in SSP1SR is lost. ; Overflow can only occur in Slave mode. ; In Slave mode, the user must read the SSP1BUF, even if only transmitting data, to avoid setting overflow. ; In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by ; writing to the SSP1BUF register (must be cleared in software). ; 0 = No overflow ; In I2 C mode: ; 1 = A byte is received while the SSP1BUF register is still holding the previous byte. ; SSP1OV is a gdonft careh in Transmit mode (must be cleared in software). ; 0 = No overflow ; SSP1CON1[5] SSP1EN: Synchronous Serial Port Enable bit ; In both modes, when enabled, these pins must be properly configured as input or output ; In SPI mode: ; 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) ; 0 = Disables serial port and configures these pins as I/O port pins ; In I2 C mode: ; 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) ; 0 = Disables serial port and configures these pins as I/O port pins ; SSP1CON1[4] CKP: Clock Polarity Select bit ; In SPI mode: ; 1 = Idle state for clock is a high level ; 0 = Idle state for clock is a low level ; In I2 C Slave mode: ; SCL release control ; 1 = Enable clock ; 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) ; In I2 C Master mode: Unused in this mode ; SSP1CON1[3-0] SSP1M<3:0>: Synchronous Serial Port Mode Select bits ; 0000 = SPI Master mode, clock = FOSC/4 ; 0001 = SPI Master mode, clock = FOSC/16 ; 0010 = SPI Master mode, clock = FOSC/64 ; 0011 = SPI Master mode, clock = TMR2 output/2 ; 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled ; 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin ; 0110 = I2C Slave mode, 7-bit address ; 0111 = I2C Slave mode, 10-bit address ; 1000 = I2C Master mode, clock = FOSC / (4 * (SSP1ADD+1))(4) ; 1001 = Reserved ; 1010 = SPI Master mode, clock = FOSC/(4 * (SSP1ADD+1)) ; 1011 = I2C firmware controlled Master mode (Slave idle) ; 1100 = Reserved ; 1101 = Reserved ; 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled ; 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled ; Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSP1BUF register. ; 2: When enabled, these pins must be properly configured as input or output. ; 3: When enabled, the SDA and SCL pins must be configured as inputs. ; 4: SSP1ADD values of 0, 1 or 2 are not supported for I2C Mode. ; ******************************************************* SELBANK 4 MOVLW B'00101000' MOVWF SSP1CON1 ; ******************************************************* ; 3.Define SSP1CON2: SSP1 CONTROL REGISTER 2 (BANK4) ; SSP1CON2[7] GCEN: General Call Enable bit (in I2C Slave mode only) ; 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR ; 0 = General call address disabled ; SSP1CON2[6] ACKSTAT: Acknowledge Status bit (in I2C mode only) ; 1 = Acknowledge was not received ; 0 = Acknowledge was received ; SSP1CON2[5] ACKDT: Acknowledge Data bit (in I2C mode only) ; In Receive mode: ; Value transmitted when the user initiates an Acknowledge sequence at the end of a receive ; 1 = Not Acknowledge / 0 = Acknowledge ; SSP1CON2[4] ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) ; In Master Receive mode: ; 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. ; Automatically cleared by hardware. ; 0 = Acknowledge sequence idle ; SSP1CON2[3] RCEN: Receive Enable bit (in I2C Master mode only) ; 1 = Enables Receive mode for I2C ; 0 = Receive idle ; SSP1CON2[2] PEN: Stop Condition Enable bit (in I2C Master mode only) ; SCK Release Control: ; 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. ; 0 = Stop condition Idle ; SSP1CON2[1] RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) ; 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. ; 0 = Repeated Start condition Idle ; SSP1CON2[0] SEN: Start Condition Enabled bit (in I2C Master mode only) ; In Master mode: ; 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. ; 0 = Start condition Idle ; In Slave mode: ; 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) ; 0 = Clock stretching is disabled ; Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be ; set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled). ; ******************************************************* SELBANK 4 MOVLW B'00000000' MOVWF SSP1CON2 ; ******************************************************* ; 4.Define SSP1CON3: SSP1 CONTROL REGISTER 3 (BANK4) ; SSP1CON3[7] ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) ; 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock ; 0 = Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock ; SSP1CON3[6] PCIE: Stop Condition Interrupt Enable bit (I2C mode only) ; 1 = Enable interrupt on detection of Stop condition ; 0 = Stop detection interrupts are disabled(2) ; SSP1CON3[5] SCIE: Start Condition Interrupt Enable bit (I2C mode only) ; 1 = Enable interrupt on detection of Start or Restart conditions ; 0 = Start detection interrupts are disabled(2) ; SSP1CON3[4] BOEN: Buffer Overwrite Enable bit ; In SPI Slave mode:(1) ; 1 = SSP1BUF updates every time that a new data byte is shifted in ignoring the BF bit ; 0 = If new byte is received with BF bit of the SSP1STAT register already set, SSP1OV bit of the SSP1CON1 register is set, and the buffer is not updated ; In I2C Master mode and SPI Master mode: This bit is ignored. ; In I2C Slave mode: ; 1 = SSP1BUF is updated and ACK is generated for a received address/data byte, ignoring the ; state of the SSP1OV bit only if the BF bit = 0. ; 0 = SSP1BUF is only updated when SSP1OV is clear ; SSP1CON3[3] SDAHT: SDA Hold Time Selection bit (I2C mode only) ; 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL ; 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL ; SSP1CON3[2] SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) ; If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the ; BCL1IF bit of the PIR2 register is set, and bus goes idle ; 1 = Enable slave bus collision interrupts ; 0 = Slave bus collision interrupts are disabled ; SSP1CON3[1] AHEN: Address Hold Enable bit (I2C Slave mode only) ; 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the ; SSP1CON1 register will be cleared and the SCL will be held low. ; 0 = Address holding is disabled ; SSP1CON3[0] DHEN: Data Hold Enable bit (I2C Slave mode only) ; 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit ; of the SSP1CON1 register and SCL is held low. ; 0 = Data holding is disabled ; Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSP1OV is still set ; when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSP1BUF. ; 2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. ; 3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. ; ******************************************************* SELBANK 4 MOVLW B'00000000' MOVWF SSP1CON3 ; ******************************************************* ; 5.Define SSP1MSK: SSP1 MASK REGISTER (BANK4) ; SSP1MSK[7-1] MSK<7:1>: Mask bits ; 1 = The received address bit n is compared to SSP1ADD to detect I2C address match ; 0 = The received address bit n is not used to detect I2C address match ; SSP1MSK[0] MSK<0>: Mask bit for I2C Slave mode, 10-bit Address ; I2C Slave mode, 10-bit address (SSP1M<3:0> = 0111 or 1111): ; 1 = The received address bit 0 is compared to SSP1ADD<0> to detect I2C address match ; 0 = The received address bit 0 is not used to detect I2C address match ; I2C Slave mode, 7-bit address, the bit is ignored ; ******************************************************* SELBANK 4 MOVLW B'00000000' MOVWF SSP1MSK ; ******************************************************* ; 6.Define SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I2C MODE) (BANK4) ; Master mode: ; SSP1ADD[7-0] ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC ; 10-Bit Slave mode ? Most Significant Address byte: ; SSP1ADD[7-3] Not used: Unused for Most Significant Address byte. ; Bit state of this register is a gdonft careh. ; Bit pattern sent by master is fixed by I2C specification and must be equal to e11110f. ; However, those bits are compared by hardware and are not affected by the value in this register. ; SSP1ADD[2-1] ADD<2:1>: Two Most Significant bits of 10-bit address ; SSP1ADD[0] Not used: Unused in this mode. Bit state is a gdonft careh. ; 10-Bit Slave mode ? Least Significant Address byte: ; SSP1ADD[7-0] ADD<7:0>: Eight Least Significant bits of 10-bit address ; 7-Bit Slave mode: ; SSP1ADD[7-1] ADD<7:1>: 7-bit address ; SSP1ADD[0] Not used: Unused in this mode. Bit state is a gdonft careh. ; ******************************************************* ; BAUD RATE ; Fosc:16(MHz) ; 16000000 / ( 0x27(0d39) + 1 ) / 4(PIC) ==> 100KHz SELBANK 4 MOVLW H'27' ; See Manual p.273 (Fosc:16MHz, Fclock:100KHz) MOVWF SSP1ADD SELBANK 0 RETURN ;****************************************************************************************** ; Program : PUTI2CSTR ; Title : Issue the start condition and trancemission address ; Input : ; Output : ; Description : ;****************************************************************************************** PUTI2CSTR ; ***************************** ; 1.Start condition and trancemission address ; ***************************** ; (1)Start condition SELBANK 4 BSF SSP1CON2,SEN BTFSC SSP1CON2,SEN GOTO $-1 ; (2)Check SSPIF SELBANK 0 BTFSS PIR1,SSP1IF GOTO $-1 ; (3)SSP1IF is cleared SELBANK 0 BCF PIR1,SSP1IF ; (4)User loads the SSP1BUFF SELBANK 4 MOVFW I2C_DAT MOVWF SSP1BUF ; (5)Check ACKSTAT SELBANK 4 BTFSC SSP1CON2,ACKSTAT GOTO $-1 SELBANK 0 RETURN ;****************************************************************************************** ; Program : PUTI2CSTP ; Title : Issue the stop condition ; Input : ; Output : ; Description : ;****************************************************************************************** PUTI2CSTP ; (1)Check SSPIF and clear SELBANK 0 BTFSS PIR1,SSP1IF GOTO $-1 BCF PIR1,SSP1IF ; (2)Stop condition SELBANK 4 BSF SSP1CON2,PEN ; (3)Check SSPIF and clear SELBANK 0 BTFSS PIR1,SSP1IF GOTO $-1 BCF PIR1,SSP1IF SELBANK 0 RETURN ;****************************************************************************************** ; Program : PUTI2CDAT ; Title : Put I2C data ; Input : ; Output : ; Description : ;****************************************************************************************** PUTI2CDAT ; ***************************** ; Trancemission data ; ***************************** ; (1)Check SSPIF SELBANK 0 BTFSS PIR1,SSP1IF GOTO $-1 ; (2)SSP1IF is cleared SELBANK 0 BCF PIR1,SSP1IF ; (3)User loads the SSP1BUFF SELBANK 4 MOVFW I2C_DAT MOVWF SSP1BUF ; (4)Check ACKSTAT SELBANK 4 BTFSC SSP1CON2,ACKSTAT GOTO $-1 SELBANK 0 RETURN ;****************************************************************************************** ; Function Name : Wait_001S ; Title : This function will wait n times of 0.001 seconds ; Input : W-reg (n) ; Output : ;****************************************************************************************** WAIT_001S MOVWF TMP_C WAIT_001S_1 CALL WAIT_1MS DECFSZ TMP_C,F GOTO WAIT_001S_1 RETURN ;****************************************************************************************** ; Function Name : Wait_1mS ; Title : This function will wait 1 mS ; Input : ; Output : ;****************************************************************************************** WAIT_1MS ; ******************************************************* ; 1.Define T1CON(TIMER1 CONTROL REGISTER) Register ; T1CON(7-6) TMR1CS1,TMR1CS0: Timer1 Clock Source Select bits ; 11 =Timer1 clock source is Capacitive Sensing Oscillator (CAPOSC) ; 10 =Timer1 clock source is pin or oscillator: ; If T1OSCEN = 0: ; External clock from T1CKI pin (on the rising edge) ; If T1OSCEN = 1: ; Crystal oscillator on T1OSI/T1OSO pins ; 01 =Timer1 clock source is system clock (FOSC) ; 00 =Timer1 clock source is instruction clock (FOSC/4) ; T1CON(5-4) T1CKPS1,T1CKPS0: Timer1 Input Clock Prescale Select bits ; 11 = 1:8 Prescale value ; 10 = 1:4 Prescale value ; 01 = 1:2 Prescale value ; 00 = 1:1 Prescale value ; T1CON(3) T1OSCEN: LP Oscillator Enable Control bit ; 1 = Dedicated Timer1 oscillator circuit enabled ; 0 = Dedicated Timer1 oscillator circuit disabled ; T1CON(2) T1SYNC: Timer1 External Clock Input Synchronization Control bit ; TMR1CS1,TMR1CS0 = 1X ; 1 = Do not synchronize external clock input ; 0 = Synchronize external clock input with system clock (FOSC) ; TMR1CS1,TMR1CS0 = 0X ; This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> = 1X. ; T1CON(1) Unimplemented: Read as e0f ; T1CON(0) TMR1ON: Timer1 On bit ; 1 = Enables Timer1 ; 0 = Stops Timer1 ; Clears Timer1 Gate flip-flop ; ******************************************************* SELBANK 0 ; SET BANK0 MOVLW B'00000001' MOVWF T1CON ; ******************************************************* ; 2.Define T1GCON (TIMER1 GATE CONTROL REGISTER) Register ; T1GCON(7) TMR1GE: Timer1 Gate Enable bit ; If TMR1ON = 0: ; This bit is ignored ; If TMR1ON = 1: ; 1 = Timer1 counting is controlled by the Timer1 gate function ; 0 = Timer1 counts regardless of Timer1 gate function ; T1GCON(6) T1GPOL: Timer1 Gate Polarity bit ; 1 = Timer1 gate is active-high (Timer1 counts when gate is high) ; 0 = Timer1 gate is active-low (Timer1 counts when gate is low) ; T1GCON(5) T1GTM: Timer1 Gate Toggle Mode bit ; 1 = Timer1 Gate Toggle mode is enabled ; 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared ; Timer1 gate flip-flop toggles on every rising edge. ; T1GCON(4) T1GSPM: Timer1 Gate Single-Pulse Mode bit ; 1 = Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate ; 0 = Timer1 gate Single-Pulse mode is disabled ; T1GCON(3) T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit ; 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge ; 0 = Timer1 gate single-pulse acquisition has completed or has not been started ; This bit is automatically cleared when T1GSPM is cleared. ; T1GCON(2) T1GVAL: Timer1 Gate Current State bit ; Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. ; Unaffected by Timer1 Gate Enable (TMR1GE). ; T1GCON(1-0) T1GSS1,T1GSS0: Timer1 Gate Source Select bits ; 00 = Timer1 Gate pin ; 01 = Timer0 overflow output ; 10 = Comparator 1 optionally synchronized output (SYNCC1OUT) ; 11 = Comparator 2 optionally synchronized output (SYNCC2OUT) ; ******************************************************* MOVLW B'00000000' MOVWF T1GCON ; ******************************************************* ; 3.Define TMR1 Register ; ******************************************************* ; TMR1 data ( OSC:16MHz, FOSC/4, 1:8 Prescale value, 0.01[S];100Hz ) ; 10mS(100Hz): 16MHz / 4(FOSC/4) / 8(Prescale) / 100(100Hz)==> 0d5,000(Count) ==> 0x1388(Count) ; TMR1 = 0xFFFF - 0x1388 ==> 0xEC77 ; TMR1 data ( OSC:16MHz, FOSC/4, 1:8 Prescale value, 0.1[S];10Hz ) ; 100mS(10Hz): 16MHz / 4(FOSC/4) / 8(Prescale) / 10(10Hz) ==> 0d50,000(Count) ==> 0xC350(Count) ; TMR1 = 0xFFFF - 0xC350 ==> 0x3CAF ; TMR1 data ( OSC:16MHz, FOSC/4, 1:1 Prescale value, 0.001[S];1000Hz ) ; 100mS(10Hz): 16MHz / 4(FOSC/4) / 1(Prescale) / 1000(1000Hz) ==> 0d4000(Count) ==> 0xFA0(Count) ; TMR1 = 0xFFFF - 0x0FA0 ==> 0xF05F MOVLW H'F0' MOVWF TMR1H MOVLW H'5F' MOVWF TMR1L ; ******************************************************* ; 4.Timer ; ******************************************************* BCF PIR1,TMR1IF BTFSS PIR1,TMR1IF GOTO $-1 RETURN END