//****************************************************************************************** // PIC18F25K22 Sample Program // Project : // Program Name : // Programer : // Create date : Version 1.0 R06.06.10 // History : // Laungage : XC8 C Laungage Version 2.41 // Environment : Microchip MPLAB X IDE v6.05 / PICKIT3 or PICKIT4 / Windows 10 or 11 //****************************************************************************************** // (1)Description // Internal OSC 64MHz : 16MHz * 4 (PLL) //****************************************************************************************** #include #include #include #include #include #include // ========================================= // Config words for PIC18F25K22 // ========================================= // 1.Examples // Oscillator Selection bits : EC oscillator (high power, >16 MHz) // 4X PLL Enable : Oscillator used directly // Primary clock enable bit : Primary clock enabled // Fail-Safe Clock Monitor Enable bit : Fail-Safe Clock Monitor disabled // Internal/External Oscillator Switchover bit : Oscillator Switchover mode disabled ////#pragma config FOSC = ECHPIO6, PLLCFG = OFF, PRICLKEN = ON, FCMEN = OFF, IESO = OFF // // 2.Config word for sample program #pragma config FOSC=INTIO67 //Internal oscillator block //#pragma config PLLCFG=ON //Oscillator multiplied by 4 #pragma config PLLCFG=OFF //Oscillator multiplied by 4 #pragma config PRICLKEN=OFF //Primary clock enabled #pragma config FCMEN=OFF //Fail-Safe Clock Monitor disabled #pragma config IESO=OFF //Oscillator Switchover mode disabled #pragma config PWRTEN=ON //Power up timer enabled #pragma config BOREN=ON //Brown-out Reset disabled in hardware and software #pragma config BORV=190 //VBOR set to 1.95 V nominal #pragma config WDTEN=ON //WDT is always enabled. SWDTEN bit has no effect //#pragma config WDTEN=OFF //WDT is always enabled. SWDTEN bit has no effect #pragma config WDTPS=32768 //Watchdog Timer Postscale Select bits (1:32768) #pragma config CCP2MX=PORTC1 //CCP2 input/output is multiplexed with RC1 #pragma config PBADEN=OFF //PORTB<5:0> pins are configured as digital I/O on Reset #pragma config CCP3MX=PORTB5 //P3A/CCP3 input/output is multiplexed with RB5 #pragma config HFOFST=OFF //HFINTOSC output and ready status are delayed by the oscillator stable status #pragma config T3CMX=PORTC0 //T3CKI is on RC0 #pragma config P2BMX=PORTB5 //P2B is on RB5 #pragma config MCLRE=EXTMCLR //MCLR pin enabled, RE3 input pin disabled #pragma config CP0=OFF //Block 0 not code-protected #pragma config CP1=OFF //Block 1 not code-protected #pragma config CP2=OFF //Block 2 not code-protected #pragma config CP3=OFF //Block 3 not code-protected #pragma config CPB=OFF //Boot block (000000-0007FFh) not code-protected #pragma config CPD=OFF //Data EEPROM not code-protected #pragma config WRT0=OFF //Block 0 not write-protected #pragma config WRT1=OFF //Block 1 not write-protected #pragma config WRT2=OFF //Block 2 not write-protected #pragma config WRT3=OFF //Block 3 not write-protected #pragma config WRTC=OFF //Configuration registers (300000-3000FFh) not write-protected #pragma config WRTB=OFF //Boot Block (000000-0007FFh) not write-protected #pragma config WRTD=OFF //Data EEPROM not write-protected #pragma config EBTR0=OFF //Block 0 not protected from table reads executed in other blocks #pragma config EBTR1=OFF //Block 1 not protected from table reads executed in other blocks #pragma config EBTR2=OFF //Block 2 not protected from table reads executed in other blocks #pragma config EBTR3=OFF //Block 3 not protected from table reads executed in other blocks #pragma config EBTRB=OFF //Boot Block (000000-0007FFh) not protected from table reads executed in other blocks // #define PI_NORMAL 0 #define PI_FAILER 1 #define PI_ADC_0 2 #define PI_ADC_1 3 #define PI_ADC_2 4 #define P_TEST_LED1 PORTCbits.RC4 // void Wait_1S(unsigned int) ; void Wait_1mS(unsigned int) ; void Timer_1mS(void) ; void Init_OSC(void) ; void Init_PORT_ATTRIBUTE(void) ; void Init_ADC(void) ; void User_CLRWDT(void) ; void Init_usart(void) ; char Recive_usart1(char *) ; char Recive_usart2(char *) ; char Send_usart1(char) ; char Send_usart2(char) ; void Send_usart1_s(char *) ; void Send_usart2_s(char *) ; void Send_usart1_int(unsigned int) ; void Send_usart2_int(unsigned int) ; void Send_usart1_long(unsigned long int) ; void Send_usart2_long(unsigned long int) ; void Send_usart1_CR(void) ; void Send_usart2_CR(void) ; void Init_ADC(void) ; unsigned int Get_ADC(char) ; void Test_0001(void) ; // ========================================= // Program main // ========================================= void main(void) { unsigned char lp; // ***************************** // 1.Initialized // ***************************** // (1)Define OSC Init_OSC(); //Internal OSC 16MHz // (2)Define PORT Attribute Init_PORT_ATTRIBUTE(); // (3)Define I/O port TRISA = 0b11111111; TRISB = 0b11111111; TRISC = 0b10000000; LATC = 0b00000000; PORTA = 0x00; PORTB = 0x00; PORTC = 0x00; // (4)Define EUSART Init_usart(); // (5)Define ADC Init_ADC(); // (6)Demo LED Wait_1mS(100) ; Send_usart1_s("Program started 1 !!!! ") ; Send_usart2_s("Program started 2 !!!! ") ; Test_0001(); // ***************************** // 2.Program main // ***************************** } //****************************************************************************************** // Program : Test_0001 // Title : // Input : // Output : // Description : //****************************************************************************************** void Test_0001(void) { unsigned int adc_data ; while(1){ adc_data = Get_ADC(PI_ADC_0) ; Send_usart1_s("ADC0:") ; Send_usart1_int(adc_data) ; User_CLRWDT() ; // adc_data = Get_ADC(PI_ADC_1) ; Send_usart1_s(" ADC1:") ; Send_usart1_int(adc_data) ; User_CLRWDT() ; // adc_data = Get_ADC(PI_ADC_2) ; Send_usart1_s(" ADC2:") ; Send_usart1_int(adc_data) ; User_CLRWDT() ; // Send_usart1_CR() ; Wait_1S(1) ; } } //****************************************************************************************** // Program : Init_OSC // Title : Initiarized system clock (Internal OSC 64MHz : 16MHz * 4) // Input : // Output : // Description : //****************************************************************************************** void Init_OSC(void) { // ****************************************************************** // 1.Define OSCCON: OSCILLATOR CONTROL REGISTER // OSCCON[7] IDLEN: Idle Enable bit // 1 = Device enters Idle mode on SLEEP instruction // 0 = Device enters Sleep mode on SLEEP instruction // OSCCON[6-4] IRCF<2:0>: Internal RC Oscillator Frequency Select bits(2) // 111 = HFINTOSC (16 MHz) // 110 = HFINTOSC/2 (8 MHz) // 101 = HFINTOSC/4 (4 MHz) // 100 = HFINTOSC/8 (2 MHz) // 011 = HFINTOSC/16 (1 MHz)(3) // If INTSRC = 0 and MFIOSEL = 0: // 010 = HFINTOSC/32 (500 kHz) // 001 = HFINTOSC/64 (250 kHz) // 000 = LFINTOSC (31.25 kHz) // If INTSRC = 1 and MFIOSEL = 0: // 010 = HFINTOSC/32 (500 kHz) // 001 = HFINTOSC/64 (250 kHz) // 000 = HFINTOSC/512 (31.25 kHz) // If INTSRC = 0 and MFIOSEL = 1: // 010 = MFINTOSC (500 kHz) // 001 = MFINTOSC/2 (250 kHz) // 000 = LFINTOSC (31.25 kHz) // If INTSRC = 1 and MFIOSEL = 1: // 010 = MFINTOSC (500 kHz) // 001 = MFINTOSC/2 (250 kHz) // 000 = MFINTOSC/16 (31.25 kHz) // OSCCON[3] OSTS: Oscillator Start-up Time-out Status bit // 1 = Device is running from the clock defined by FOSC<3:0> of the CONFIG1H register // 0 = Device is running from the internal oscillator (HFINTOSC, MFINTOSC or LFINTOSC) // OSCCON[2] HFIOFS: HFINTOSC Frequency Stable bit // 1 = HFINTOSC frequency is stable // 0 = HFINTOSC frequency is not stable // OSCCON[1-0] SCS<1:0>: System Clock Select bit // 1x = Internal oscillator block // 01 = Secondary (SOSC) oscillator // 00 = Primary clock (determined by FOSC<3:0> in CONFIG1H). // ****************************************************************** OSCCON = 0b01110000; // ****************************************************************** // 2.Define OSCCON2: OSCILLATOR CONTROL REGISTER 2 // OSCCON2[7] PLLRDY: PLL Run Status bit // 1 = System clock comes from 4xPLL // 0 = System clock comes from an oscillator, other than 4xPLL // OSCCON2[6] SOSCRUN: SOSC Run Status bit // 1 = System clock comes from secondary SOSC // 0 = System clock comes from an oscillator, other than SOSC // OSCCON2[5] Unimplemented: Read as 0 // OSCCON2[4] MFIOSEL: MFINTOSC Select bit // 1 = MFINTOSC is used in place of HFINTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz // 0 = MFINTOSC is not used // OSCCON2[3] SOSCGO(1): Secondary Oscillator Start Control bit // 1 = Secondary oscillator is enabled. // 0 = Secondary oscillator is shut off if no other sources are requesting it. // OSCCON2[2] PRISD: Primary Oscillator Drive Circuit Shutdown bit // 1 = Oscillator drive circuit on // 0 = Oscillator drive circuit off (zero power) // OSCCON2[1] MFIOFS: MFINTOSC Frequency Stable bit // 1 = MFINTOSC is stable // 0 = MFINTOSC is not stable // OSCCON2[0] LFIOFS: LFINTOSC Frequency Stable bit // 1 = LFINTOSC is stable // 0 = LFINTOSC is not stable // ****************************************************************** OSCCON2 = 0b10000000; // ****************************************************************** // 3.Define OSCTUNE: OSCILLATOR TUNING REGISTER // OSCTUNE[7] INTSRC: Internal Oscillator Low-Frequency Source Select bit // 1 = 31.25 kHz device clock derived from the MFINTOSC or HFINTOSC source // 0 = 31.25 kHz device clock derived directly from LFINTOSC internal oscillator // OSCTUNE[6] PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit(1) // 1 = PLL enabled for HFINTOSC (8 MHz and 16 MHz only) // 0 = PLL disabled // OSCTUNE[5-0] TUN<5:0>: Frequency Tuning bits - use to adjust MFINTOSC and HFINTOSC frequencies // 011111 = Maximum frequency // 011110 = // ......... // 000001 = // 000000 = Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated frequency. // 111111 = // ......... // 100000 = Minimum frequency // ****************************************************************** OSCTUNE = OSCTUNE | 0b01000000 ; } //****************************************************************************************** // Function Name : Init_PORT_ATTRIBUTE // Title : // Input : // Output : // Description : //****************************************************************************************** void Init_PORT_ATTRIBUTE(void) { // ****************************************************************** // 1.Define ANSELA PORTA ANALOG SELECT REGISTER // ANSELA[7-6] Unimplemented: Read as 0™ // ANSELA[5] ANSA5: RA5 Analog Select bit // 1 = Digital input buffer disabled // 0 = Digital input buffer enabled // ANSELA[4] Unimplemented: Read as 0 // ANSELA[3-0] ANSA<3:0>: RA<3:0> Analog Select bit // 1 = Digital input buffer disabled // 0 = Digital input buffer enabled // // 7 6 5 4 3 2 1 0 // (-) (-) (ANSA5) (-) (ANSA3) (ANSA2) (ANSA1) (ANSA0) // ****************************************************************** ANSELA = 0b00000111; // ****************************************************************** // 2.Define ANSELB PORTB ANALOG SELECT REGISTER // ANSELB[7-6] Unimplemented: Read as 0 // ANSELB[5-0] ANSB<5:0>: RB<5:0> Analog Select bit // 1 = Digital input buffer disabled // 0 = Digital input buffer enabled // // 7 6 5 4 3 2 1 0 // (-) (-) (ANSB5) (ANSB4) (ANSB3) (ANSB2) (ANSB1) (ANSB0) // ****************************************************************** ANSELB = 0b00000000; // ****************************************************************** // 3.Define ANSELC PORTC ANALOG SELECT REGISTER // ANSELC[7-2] ANSC<7:2>: RC<7:2> Analog Select bit // 1 = Digital input buffer disabled // 0 = Digital input buffer enabled // ANSELC[1-0] Unimplemented: Read as 0 // // 7 6 5 4 3 2 1 0 // (ANSC7) (ANSC6) (ANSC5) (ANSC4) (ANSC3) (ANSC2) (-) (-) // ****************************************************************** ANSELC = 0b00000000; // ****************************************************************** // 4.Define ANSELD PORTD ANALOG SELECT REGISTER // ANSELD[7-0] ANSD<7:0>: RD<7:0> Analog Select bit // 1 = Digital input buffer disabled // 0 = Digital input buffer enabled // // 7 6 5 4 3 2 1 0 // (ANSD7) (ANSD6) (ANSD5) (ANSD4) (ANSD3) (ANSD2) (ANSD1) (ANSD0) // ****************************************************************** // ANSELD = 0b00000000; // ****************************************************************** // 5.ANSELE PORTE ANALOG SELECT REGISTER // ANSELE[7-3] Unimplemented: Read as 0 // ANSELE[2-0] ANSE<2:0>: RE<2:0> Analog Select bit(1) // 1 = Digital input buffer disabled // 0 = Digital input buffer enabled // // 7 6 5 4 3 2 1 0 // (-) (-) (-) (-) (-) ANSE2(1) ANSE1(1) ANSE0(1) // ****************************************************************** // ANSELE = 0b00000000; } //****************************************************************************************** // Program : Wait_1S // Title : A 1S timer that specifies the number of times // Input : // Output : // Description : //****************************************************************************************** void Wait_1S(unsigned int timer_n) { unsigned int lp; for(lp=0;lp: Timer1/3/5 Clock Source Select bits // 11 =Reserved. Do not use. // 10 =Timer1/3/5 clock source is pin or oscillator: // If TxSOSCEN = 0: // External clock from TxCKI pin (on the rising edge) // If TxSOSCEN = 1: // Crystal oscillator on SOSCI/SOSCO pins // 01 =Timer1/3/5 clock source is system clock (FOSC) // 00 =Timer1/3/5 clock source is instruction clock (FOSC/4) // T1CON[5-4] TxCKPS<1:0>: Timer1/3/5 Input Clock Prescale Select bits // 11 = 1:8 Prescale value // 10 = 1:4 Prescale value // 01 = 1:2 Prescale value // 00 = 1:1 Prescale value // T1CON[3] TxSOSCEN: Secondary Oscillator Enable Control bit // 1 = Dedicated Secondary oscillator circuit enabled // 0 = Dedicated Secondary oscillator circuit disabled // T1CON[2] TxSYNC: Timer1/3/5 External Clock Input Synchronization Control bit // TMRxCS<1:0> = 1X // 1 = Do not synchronize external clock input // 0 = Synchronize external clock input with system clock (FOSC) // TMRxCS<1:0> = 0X // This bit is ignored. Timer1/3/5 uses the internal clock when TMRxCS<1:0> = 1X. // T1CON[1] TxRD16: 16-Bit Read/Write Mode Enable bit // 1 = Enables register read/write of Timer1/3/5 in one 16-bit operation // 0 = Enables register read/write of Timer1/3/5 in two 8-bit operation // T1CON[0] TMRxON: Timer1/3/5 On bit // 1 = Enables Timer1/3/5 // 0 = Stops Timer1/3/5 // Clears Timer1/3/5 Gate flip-flop // ****************************************************************** T1CON = 0b01110011; // ****************************************************************** // 2.Define T1GCON: TIMER1 GATE CONTROL REGISTER for PIC18F25K22 // T1GCON[7] TMRxGE: Timer1/3/5 Gate Enable bit // If TMRxON = 0: // This bit is ignored // If TMRxON = 1: // 1 = Timer1/3/5 counting is controlled by the Timer1/3/5 gate function // 0 = Timer1/3/5 counts regardless of Timer1/3/5 gate function // T1GCON[6] TxGPOL: Timer1/3/5 Gate Polarity bit // 1 = Timer1/3/5 gate is active-high (Timer1/3/5 counts when gate is high) // 0 = Timer1/3/5 gate is active-low (Timer1/3/5 counts when gate is low) // T1GCON[5] TxGTM: Timer1/3/5 Gate Toggle Mode bit // 1 = Timer1/3/5 Gate Toggle mode is enabled // 0 = Timer1/3/5 Gate Toggle mode is disabled and toggle flip-flop is cleared // Timer1/3/5 gate flip-flop toggles on every rising edge. // T1GCON[4] TxGSPM: Timer1/3/5 Gate Single-Pulse Mode bit // 1 = Timer1/3/5 gate Single-Pulse mode is enabled and is controlling Timer1/3/5 gate // 0 = Timer1/3/5 gate Single-Pulse mode is disabled // T1GCON[3] TxGGO/DONE: Timer1/3/5 Gate Single-Pulse Acquisition Status bit // 1 = Timer1/3/5 gate single-pulse acquisition is ready, waiting for an edge // 0 = Timer1/3/5 gate single-pulse acquisition has completed or has not been started // This bit is automatically cleared when TxGSPM is cleared. // T1GCON[2] TxGVAL: Timer1/3/5 Gate Current State bit // Indicates the current state of the Timer1/3/5 gate that could be provided to TMRxH:TMRxL. // Unaffected by Timer1/3/5 Gate Enable (TMRxGE). // T1GCON[1-0] TxGSS<1:0>: Timer1/3/5 Gate Source Select bits // 00 = Timer1/3/5 Gate pin // 01 = Timer2/4/6 Match PR2/4/6 output (See Table 12-6 for proper timer match selection) // 10 = Comparator 1 optionally synchronized output (SYNCC1OUT) // 11 = Comparator 2 optionally synchronized output (SYNCC2OUT) // ****************************************************************** T1GCON = 0b00000000; // ****************************************************************** // 3.Define TMR1 Register // (1)TMR1 data ( OSC:64MHz, 1:8 Prescale value, 0.001[S];1000Hz ) // 1mS(1000Hz): 64MHz / 8(Prescale value) /1000(1000Hz)==> 0d8000(Count) ==> 0x1F40(Count) // TMR1 = 0xFFFF - 0x1F40 ==> 0xE0BF // (2)TMR1 data ( OSC:16MHz, 1:8 Prescale value, 0.001[S];1000Hz ) // 1mS(1000Hz): 16MHz / 8(Prescale value) /1000(1000Hz)==> 0d2000(Count) ==> 0x7D0(Count) // TMR1 = 0xFFFF - 0x07D0 ==> 0xF82F // ****************************************************************** TMR1H = 0xE0; TMR1L = 0xBF; // // TMR1H = 0xFE; // TMR1L = 0x0B; // ****************************************************************** // 4.Timer // ****************************************************************** PIR1bits.TMR1IF = 0; while(1){ if(PIR1bits.TMR1IF != 0 )break; } } //****************************************************************************************** // Function Name : Init_ADC // Title : // Input : // Output : // Description : //****************************************************************************************** void Init_ADC(void) { // ****************************************************************** // 1.Define ADCON0: A/D CONTROL REGISTER 0 // ADCON0[7] Unimplemented: Read as 0 // ADCON0[6-2] CHS<4:0>: Analog Channel Select bits // 00000 = AN0 // 00001 = AN1 // 00010 = AN2 // 00011 = AN3 // 00100 = AN4 // 00101 = AN5(1) // 00110 = AN6(1) // 00111 = AN7(1) // 01000 = AN8 // 01001 = AN9 // 01010 = AN10 // 01011 = AN11 // 01100 = AN12 // 01101 = AN13 // 01110 = AN14 // 01111 = AN15 // 10000 = AN16 // 10001 = AN17 // 10010 = AN18 // 10011 = AN19 // 10100 = AN20(1) // 10101 = AN21(1) // 10110 = AN22(1) // 10111 = AN23(1) // 11000 = AN24(1) // 11001 = AN25(1) // 11010 = AN26(1) // 11011 = AN27(1) // 11100 = Reserved // 11101 = CTMU // 11110 = DAC // 11111 = FVR BUF2 (1.024V/2.048V/2.096V Volt Fixed Voltage Reference)(2) // ADCON0[1] GO/DONE: A/D Conversion Status bit // 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. // This bit is automatically cleared by hardware when the A/D conversion has completed. // 0 = A/D conversion completed/not in progress // ADCON0[0] ADON: ADC Enable bit // 1 = ADC is enabled // 0 = ADC is disabled and consumes no operating current // ****************************************************************** ADCON0 = 0b00000001; // ****************************************************************** // 2.Define ADCON1: A/D CONTROL REGISTER 1 // ADCON1[7] TRIGSEL: Special Trigger Select bit // 1 = Selects the special trigger from CTMU // 0 = Selects the special trigger from CCP5 // ADCON1[6-4] Unimplemented: Read as 0 // ADCON1[3-2] PVCFG<1:0>: Positive Voltage Reference Configuration bits // 00 = A/D VREF+ connected to internal signal, AVDD // 01 = A/D VREF+ connected to external pin, VREF+ // 10 = A/D VREF+ connected to internal signal, FVR BUF2 // 11 = Reserved (by default, A/D VREF+ connected to internal signal, AVDD) // ADCON1[1-0] NVCFG0<1:0>: Negative Voltage Reference Configuration bits // 00 = A/D VREF- connected to internal signal, AVSS // 01 = A/D VREF- connected to external pin, VREF- // 10 = Reserved (by default, A/D VREF+ connected to internal signal, AVSS) // 11 = Reserved (by default, A/D VREF+ connected to internal signal, AVSS) // ****************************************************************** ADCON1 = 0b00000000; // ****************************************************************** // 3.Define ADCON2: A/D CONTROL REGISTER 2 // ADCON2[7] ADFM: A/D Conversion Result Format Select bit // 1 = Right justified // 0 = Left justified // ADCON2[6] Unimplemented: Read as 0 // ADCON2[5-3] ACQT<2:0>: A/D Acquisition time select bits. Acquisition time is the duration that the A/D charge holding // capacitor remains connected to A/D channel from the instant the GO/DONE bit is set until conversions begins. // 000 = 0(1) // 001 = 2 TAD // 010 = 4 TAD // 011 = 6 TAD // 100 = 8 TAD // 101 = 12 TAD // 110 = 16 TAD // 111 = 20 TAD // ADCON2[2-0] ADCS<2:0>: A/D Conversion Clock Select bits // 000 = FOSC/2 // 001 = FOSC/8 // 010 = FOSC/32 // 011 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) // 100 = FOSC/4 // 101 = FOSC/16 // 110 = FOSC/64 // 111 = FRC(1) (clock derived from a dedicated internal oscillator = 600 kHz nominal) // ****************************************************************** ADCON2 = 0b10111110 ; // ****************************************************************** // 4.Define ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 // ADRESH[7-0] ADRES<9:2>: ADC Result Register bits // Upper 8 bits of 10-bit conversion result // Define ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 // ADRESH[7-2] Reserved: Do not use. // ADRESH[1-0] ADRES<9:8>: ADC Result Register bits // Upper 2 bits of 10-bit conversion result // ****************************************************************** // ADRESH // ****************************************************************** // 5.Define ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 // ADRESL[7-6] ADRES<1:0>: ADC Result Register bits // Lower 2 bits of 10-bit conversion result // ADRESL[5-0] Reserved: Do not use. // Define ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 // ADRESL[7-0] ADRES<7:0>: ADC Result Register bits // Lower 8 bits of 10-bit conversion result // ****************************************************************** // ADRESL } //****************************************************************************************** // Function Name : Get_ADC // Title : // Input : // Output : // Description : //****************************************************************************************** unsigned int Get_ADC(char port_no) { // ****************************************************************** // 1.Define ADCON0: A/D CONTROL REGISTER 0 // ADCON0[7] Unimplemented: Read as 0 // ADCON0[6-2] CHS<4:0>: Analog Channel Select bits // 00000 = AN0 // 00001 = AN1 // 00010 = AN2 // 00011 = AN3 // 00100 = AN4 // 00101 = AN5(1) // 00110 = AN6(1) // 00111 = AN7(1) // 01000 = AN8 // 01001 = AN9 // 01010 = AN10 // 01011 = AN11 // 01100 = AN12 // 01101 = AN13 // 01110 = AN14 // 01111 = AN15 // 10000 = AN16 // 10001 = AN17 // 10010 = AN18 // 10011 = AN19 // 10100 = AN20(1) // 10101 = AN21(1) // 10110 = AN22(1) // 10111 = AN23(1) // 11000 = AN24(1) // 11001 = AN25(1) // 11010 = AN26(1) // 11011 = AN27(1) // 11100 = Reserved // 11101 = CTMU // 11110 = DAC // 11111 = FVR BUF2 (1.024V/2.048V/2.096V Volt Fixed Voltage Reference)(2) // ADCON0[1] GO/DONE: A/D Conversion Status bit // 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. // This bit is automatically cleared by hardware when the A/D conversion has completed. // 0 = A/D conversion completed/not in progress // ADCON0[0] ADON: ADC Enable bit // 1 = ADC is enabled // 0 = ADC is disabled and consumes no operating current // ****************************************************************** // (1)Set adc if( port_no == PI_ADC_0 ){ ADCON0 = 0b00000011 ; }else if( port_no == PI_ADC_1 ){ ADCON0 = 0b00000111 ; }else{ ADCON0 = 0b00001011 ; } // (2)Check adc while((ADCON0 & 0b00000010)!=0x00); // (3)Get adc value return(ADRESH * 0xff + ADRESL); } ; //****************************************************************************************** // Function Name : Send_usart1_CR // Title : // Input : // Output : // Description : //****************************************************************************************** void Send_usart1_CR(void) { Send_usart1(0x0d) ; Send_usart1(0x0a) ; } //****************************************************************************************** // Function Name : Send_usart2_CR // Title : // Input : // Output : // Description : //****************************************************************************************** void Send_usart2_CR(void) { Send_usart2(0x0d) ; Send_usart2(0x0a) ; } //****************************************************************************************** // Function Name : Send_usart1_int // Title : Send UART1 Integer // Input : // Output : // Description : //****************************************************************************************** void Send_usart1_int(unsigned int in_data) { unsigned char tmp_line[10] ; sprintf(tmp_line,"%d",in_data); Send_usart1_s(tmp_line) ; } //****************************************************************************************** // Function Name : Send_usart2_int // Title : Send UART2 Integer // Input : // Output : // Description : //****************************************************************************************** void Send_usart2_int(unsigned int in_data) { unsigned char tmp_line[10] ; sprintf(tmp_line,"%d",in_data); Send_usart2_s(tmp_line) ; } //****************************************************************************************** // Function Name : Send_usart1_long int // Title : Send UART2 Long // Input : // Output : // Description : //****************************************************************************************** void Send_usart1_long(unsigned long int in_data) { unsigned char tmp_line[20] ; sprintf(tmp_line,"%ld",in_data); Send_usart1_s(tmp_line) ; } //****************************************************************************************** // Function Name : Send_usart2_long int // Title : Send UART2 Long // Input : // Output : // Description : //****************************************************************************************** void Send_usart2_long(unsigned long int in_data) { unsigned char tmp_line[20] ; sprintf(tmp_line,"%ld",in_data); Send_usart2_s(tmp_line) ; } //****************************************************************************************** // Function Name : Send_usart1_s // Title : Send UART1 String // Input : // Output : // Description : //****************************************************************************************** void Send_usart1_s(char *put_string) { while(*put_string!=0x00){ Send_usart1(*put_string) ; put_string++ ; User_CLRWDT() ; } } //****************************************************************************************** // Function Name : Send_usart2_s // Title : Send UART2 String // Input : // Output : // Description : //****************************************************************************************** void Send_usart2_s(char *put_string) { while(*put_string!=0x00){ Send_usart2(*put_string) ; put_string++ ; User_CLRWDT() ; } } //****************************************************************************************** // Program : Init_usart // Title : // Input : // Output : // Description : //****************************************************************************************** void Init_usart(void) { //******************************************************* // 1.Define PMD0: PERIPHERAL MODULE DISABLE REGISTER 0 // PMD0[7] UART2MD: UART2 Peripheral Module Disable Control bit // 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power // 0 = Module is enabled, Clock Source is connected, module draws digital power // PMD0[6] UART1MD: UART1 Peripheral Module Disable Control bit // 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power // 0 = Module is enabled, Clock Source is connected, module draws digital power // PMD0[5] TMR6MD: Timer6 Peripheral Module Disable Control bit // 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power // 0 = Module is enabled, Clock Source is connected, module draws digital power // PMD0[4] TMR5MD: Timer5 Peripheral Module Disable Control bit // 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power // 0 = Module is enabled, Clock Source is connected, module draws digital power // PMD0[3] TMR4MD: Timer4 Peripheral Module Disable Control bit // 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power // 0 = Module is enabled, Clock Source is connected, module draws digital power // PMD0[2] TMR3MD: Timer3 Peripheral Module Disable Control bit // 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power // 0 = Module is enabled, Clock Source is connected, module draws digital power // PMD0[1] TMR2MD: Timer2 Peripheral Module Disable Control bit // 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power // 0 = Module is enabled, Clock Source is connected, module draws digital power // PMD0[0] TMR1MD: Timer1 Peripheral Module Disable Control bit // 1 = Module is disabled, Clock Source is disconnected, module does not draw digital power // 0 = Module is enabled, Clock Source is connected, module draws digital power //******************************************************* PMD0 = 0b00000000; //******************************************************* // 2.Define Interrupts //******************************************************* INTCONbits.GIE = 1 ; // Grobal Interrupt Ebable INTCONbits.PEIE = 1 ; // Peripheral Interrupt Ebable // // PIR1bits.RC1IF = 0 ; // USART1 Receive Interrupt Flag bit // PIR3bits.RC2IF = 0 ; // USART2 Receive Interrupt Flag bit // PIR1bits.TX1IF = 0 ; // USART1 Transmit Interrupt Flag bit // PIR3bits.TX2IF = 0 ; // USART2 Transmit Interrupt Flag bit // PIE1bits.RC1IE = 1 ; // USART1 Receive Interrupt Enable bit PIE3bits.RC2IE = 0 ; // USART2 Receive Interrupt Enable bit PIE1bits.TX1IE = 0 ; // USART1 Transmit Interrupt Enable bit PIE3bits.TX2IE = 0 ; // USART1 Transmit Interrupt Enable bit //******************************************************* // 3.IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 // IPR1[7] Unimplemented: Read as 0 // IPR1[6] ADIP: A/D Converter Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR1[5] RC1IP: EUSART1 Receive Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR1[4] TX1IP: EUSART1 Transmit Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR1[3] SSP1IP: Master Synchronous Serial Port 1 Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR1[2] CCP1IP: CCP1 Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR1[1] TMR2IP: TMR2 to PR2 Match Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR1[0] TMR1IP: TMR1 Overflow Interrupt Priority bit // 1 = High priority // 0 = Low priority //******************************************************* IPR1 = 0b00000000; //******************************************************* // 4.IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 // IPR3[7] SSP2IP: Synchronous Serial Port 2 Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR3[6] BCL2IP: Bus Collision 2 Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR3[5] RC2IP: EUSART2 Receive Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR3[4] TX2IP: EUSART2 Transmit Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR3[3] CTMUIP: CTMU Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR3[2] TMR5GIP: TMR5 Gate Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR3[1] TMR3GIP: TMR3 Gate Interrupt Priority bit // 1 = High priority // 0 = Low priority // IPR3[0] TMR1GIP: TMR1 Gate Interrupt Priority bit // 1 = High priority // 0 = Low priority //******************************************************* IPR3 = 0b00000000; //******************************************************* // 5.Define TXSTAX: TRANSMIT STATUS AND CONTROL REGISTER // TXSTAX[7] CSRC: Clock Source Select bit // Asynchronous mode: // Don't care // Synchronous mode: // 1 = Master mode (clock generated internally from BRG) // 0 = Slave mode (clock from external source) // TXSTAX[6] TX9: 9-bit Transmit Enable bit // 1 = Selects 9-bit transmission // 0 = Selects 8-bit transmission // TXSTAX[5] TXEN: Transmit Enable bit(1) // 1 = Transmit enabled // 0 = Transmit disabled // TXSTAX[4] SYNC: EUSART Mode Select bit // 1 = Synchronous mode // 0 = Asynchronous mode // TXSTAX[3] SENDB: Send Break Character bit // Asynchronous mode: // 1 = Send Sync Break on next transmission (cleared by hardware upon completion) // 0 = Sync Break transmission completed // Synchronous mode: // Don't care // TXSTAX[2] BRGH: High Baud Rate Select bit // Asynchronous mode: // 1 = High speed // 0 = Low speed // Synchronous mode: // Unused in this mode // TXSTAX[1] TRMT: Transmit Shift Register Status bit // 1 = TSR empty // 0 = TSR full // TXSTAX[0] TX9D: Ninth bit of Transmit Data // Can be address/data bit or a parity bit. //******************************************************* TXSTA1 = 0b00100100; TXSTA2 = 0b00100100; //******************************************************* // 6.Define RCSTAX: RECEIVE STATUS AND CONTROL REGISTER // RCSTAX[7] SPEN: Serial Port Enable bit // 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) // 0 = Serial port disabled (held in Reset) // RCSTAX[6] RX9: 9-bit Receive Enable bit // 1 = Selects 9-bit reception // 0 = Selects 8-bit reception // RCSTAX[5] SREN: Single Receive Enable bit // Asynchronous mode: // Don't care // Synchronous mode - Master: // 1 = Enables single receive // 0 = Disables single receive // This bit is cleared after reception is complete. // Synchronous mode - Slave // Don't care // RCSTAX[4] CREN: Continuous Receive Enable bit // Asynchronous mode: // 1 = Enables receiver // 0 = Disables receiver // Synchronous mode: // 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) // 0 = Disables continuous receive // RCSTAX[3] ADDEN: Address Detect Enable bit // Asynchronous mode 9-bit (RX9 = 1): // 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set // 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit // Asynchronous mode 8-bit (RX9 = 0): // Don't care // RCSTAX[2] FERR: Framing Error bit // 1 = Framing error (can be updated by reading RCREGx register and receive next valid byte) // 0 = No framing error // RCSTAX[1] OERR: Overrun Error bit // 1 = Overrun error (can be cleared by clearing bit CREN) // 0 = No overrun error // RCSTAX[0] RX9D: Ninth bit of Received Data // This can be address/data bit or a parity bit and must be calculated by user firmware. //******************************************************* RCSTA1 = 0b10010000; RCSTA2 = 0b10010000; //******************************************************* // 7.Define BAUDCONX: BAUD RATE CONTROL REGISTER // BAUDCONX[7] ABDOVF: Auto-Baud Detect Overflow bit // Asynchronous mode: // 1 = Auto-baud timer overflowed // 0 = Auto-baud timer did not overflow // Synchronous mode: // Don't care // BAUDCONX[6] RCIDL: Receive Idle Flag bit // Asynchronous mode: // 1 = Receiver is Idle // 0 = Start bit has been detected and the receiver is active // Synchronous mode: // Don't care // BAUDCONX[5] DTRXP: Data/Receive Polarity Select bit // Asynchronous mode: // 1 = Receive data (RXx) is inverted (active-low) // 0 = Receive data (RXx) is not inverted (active-high) // Synchronous mode: // 1 = Data (DTx) is inverted (active-low) // 0 = Data (DTx) is not inverted (active-high) // BAUDCONX[4] CKTXP: Clock/Transmit Polarity Select bit // Asynchronous mode: // 1 = Idle state for transmit (TXx) is low // 0 = Idle state for transmit (TXx) is high // Synchronous mode: // 1 = Data changes on the falling edge of the clock and is sampled on the rising edge of the clock // 0 = Data changes on the rising edge of the clock and is sampled on the falling edge of the clock // BAUDCONX[3] BRG16: 16-bit Baud Rate Generator bit // 1 = 16-bit Baud Rate Generator is used (SPBRGHx:SPBRGx) // 0 = 8-bit Baud Rate Generator is used (SPBRGx) // BAUDCONX[2] Unimplemented: Read as 0 // BAUDCONX[1] WUE: Wake-up Enable bit // Asynchronous mode: // 1 = Receiver is waiting for a falling edge. No character will be received but RCxIF will be set on the falling edge. // WUE will automatically clear on the rising edge. // 0 = Receiver is operating normally // Synchronous mode: // Don't care // BAUDCONX[0] ABDEN: Auto-Baud Detect Enable bit // Asynchronous mode: // 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) // 0 = Auto-Baud Detect mode is disabled // Synchronous mode: // DonIt care //******************************************************* BAUDCON1 = 0b00001000; BAUDCON2 = 0b00001000; //******************************************************* // 8.BAUD RATES (SPBRGX/SPBRGHX : EUSART Baud Rate Generator Register) // BRG 64MHz 115200BPS // BRG = 16000000(Hz)/4/9600(BPS)-1 ==> 0d0416 ==> 0x01A0 Test OK // BRG = 16000000(Hz)/4/115200(BPS)-1 ==> 0d0034 ==> 0x0022 Test OK // BRG = 64000000(Hz)/4/9600(BPS)-1 ==> 0d1666 ==> 0x0682 Test OK // BRG = 64000000(Hz)/4/115200(BPS)-1 ==> 0d0138 ==> 0x008A Test OK //******************************************************* // SPBRGH1 = 0x06; // SPBRG1 = 0x82; //9600BPS(64MHz) // SPBRGH2 = 0x06; // SPBRG2 = 0x82; //9600BPS(64MHz) SPBRGH1 = 0x00; SPBRG1 = 0x8A; //115200BPS(64MHz) SPBRGH2 = 0x00; SPBRG2 = 0x8A; //115200BPS(64MHz) } //****************************************************************************************** // Function Name : Send_usart1 // Title : // Input : // Output : // Description : //****************************************************************************************** char Send_usart1(char in_char) { char status; // *************************** // 1.Check buffer status // *************************** while(1){ if(TXSTA1bits.TRMT != 0) break; } // *************************** // 2.Set data // *************************** TXREG1 = in_char ; // **************************** // 3.Check Flag // **************************** PIR1bits.TX1IF = 0 ; while(1){ if(PIR1bits.TX1IF != 0) break; } return(PI_NORMAL) ; } //****************************************************************************************** // Function Name : Send_usart2 // Title : // Input : // Output : // Description : //****************************************************************************************** char Send_usart2(char in_char) { char status; // *************************** // 1.Check buffer status // *************************** while(1){ if(TXSTA2bits.TRMT != 0) break; } // *************************** // 2.Set data // *************************** TXREG2 = in_char ; // **************************** // 3.Check Flag // **************************** PIR3bits.TX2IF = 0 ; while(1){ if(PIR3bits.TX2IF != 0) break; } return(PI_NORMAL) ; } //****************************************************************************************** // Function Name : Recive_usart1 // Title : // Input : // Output : // Description : //****************************************************************************************** char Recive_usart1(char *io_data) { char status; // **************************** // 1.Check Recvive Flagunsigned char status; // **************************** PIR1 = PIR1 & 0b11011111 ; //00100000 (RC1IF) while(1){ status = PIR1 & 0b00100000 ; if(status != 0x00) break ; User_CLRWDT() ; } // **************************** // 2.Check error // **************************** status = RCSTA1 & 0x06; //0000,0110 RCSTA(FERR,OERR) if(status != 0x00){ *io_data = 0x00 ; return(PI_FAILER) ; } // **************************** // 3.Set Recive Data // **************************** *io_data = RCREG1 ; return(PI_NORMAL) ; } //****************************************************************************************** // Function Name : Recive_usart2 // Title : // Input : // Output : // Description : //****************************************************************************************** char Recive_usart2(char *io_data) { char status; // **************************** // 1.Check Recvive Flagunsigned char status; // **************************** PIR3 = PIR3 & 0b11011111 ; //00100000 (RC1IF) while(1){ status = PIR3 & 0b00100000 ; if(status != 0x00) break ; User_CLRWDT() ; } // **************************** // 2.Check error // **************************** status = RCSTA2 & 0x06; //0000,0110 RCSTA(FERR,OERR) if(status != 0x00){ *io_data = 0x00 ; return(PI_FAILER) ; } // **************************** // 3.Set Recive Data // **************************** *io_data = RCREG2 ; return(PI_NORMAL) ; } //****************************************************************************************** // Function Name : User_CLRWDT // Title : // Input : // Output : // Description : //****************************************************************************************** void User_CLRWDT(void) { CLRWDT(); } //****************************************************************************************** // Function Name : isr // Title : This function is the interrupt function of the PIC microcomputer . // Input : // Output : // Description : //****************************************************************************************** void __interrupt() isr(void) { char io_data; // *********************************** // 1.Echo function // *********************************** if(PIR1bits.RC1IF){ Recive_usart1(&io_data); Send_usart1(io_data) ; } }