//****************************************************************************************** // PIC32MX120F032B Sample Program // Project : // Program Name : // Programer : // Create date : Version 1.0 H24.11.17 // History : // Laungage : MPLAB C32 //****************************************************************************************** // (1)Description // Primary Oscillator 8MHz Crystal ==> PLL 40MHz (8MHz/2*20/2) //****************************************************************************************** //#include #include // //Define configration // #pragma config PMDL1WAY = OFF //Peripheral Module Disable Configuration:Allow multiple reconfigurations #pragma config IOL1WAY = OFF //Peripheral Pin Select Configuration:Allow multiple reconfigurations #pragma config FUSBIDIO = OFF //USB USID Selection:Controlled by Port Function #pragma config FVBUSONIO = OFF //USB VBUS ON Selection:Controlled by Port Function //#pragma config FPLLIDIV= DIV_1 //PLL Input Divider:1x Divider (DIV_1,DIV_2,DIV_3,DIV_4,DIV_5,DIV_6,DIV_10,DIV_12) #pragma config FPLLIDIV = DIV_2 //#pragma config FPLLMUL = MUL_15 //PLL Multiplier:15x Multiplier(MUL_15,MUL_16,MUL_17,MUL_18,MUL_19,MUL_20,MUL_21,MUL_24) #pragma config FPLLMUL = MUL_20 //#pragma config FPLLODIV= DIV_1 //System PLL Output Clock Divider:PLL Divide by 1(DIV_1,DIV_2,DIV_4,DIV_8,DIV_16,DIV_32,DIV_64,DIV_256) #pragma config FPLLODIV = DIV_2 //#pragma config FNOSC = FRC //Oscillator Selection Bits:Fast RC Osc (FRC) (FRC,FRCPLL,PRI,PRIPLL,SOSC,LPRC,FRCDIV16,FRCDIV) //#pragma config FNOSC = FRCPLL #pragma config FNOSC = PRIPLL #pragma config FSOSCEN = OFF //Secondary Oscillator Enable:Disabled #pragma config IESO = OFF //Internal/External Switch Over:Disabled //#pragma config POSCMOD = OFF //Primary Oscillator Configuration:Primary osc disabled (EC,XT,HS,OFF) ==> Used Primary Oscillator !!! #pragma config POSCMOD = HS //Primary Oscillator Configuration:Primary osc disabled (EC,XT,HS,OFF) #pragma config OSCIOFNC = OFF //CLKO Output Signal Active on the OSCO Pin::Disabled #pragma config FPBDIV = DIV_1 //Peripheral Clock Divisor:Pb_Clk is Sys_Clk/1 (DIV_1,DIV_2,DIV_4,DIV_8) #pragma config FCKSM = CSDCMD //Clock Switching and Monitor Selection:Clock Switch Disable, FSCM Disabled (CSECME,CSECMD,CSDCMD) #pragma config WDTPS = PS1 //Watchdog Timer Postscaler:1:1 (PS1,,,,PS1048576) #pragma config WINDIS = OFF //Watchdog Timer Window Enable:Watchdog Timer is in Non-Window Mode #pragma config FWDTEN = OFF //Watchdog Timer Enable:WDT Disabled (SWDTEN Bit Controls) #pragma config FWDTWINSZ = WINSZ_50//Watchdog Timer Window Size:Window Size is 50% (WINSZ_75,WINSZ_50,WINSZ_37,WISZ_25) #pragma config DEBUG = OFF //Background Debugger Enable:Debugger is Disabled #pragma config JTAGEN = OFF //JTAG Enable:JTAG Disabled #pragma config ICESEL = RESERVED//ICE/ICD Comm Channel Select:Reserved (RESERVED,ICS_PGx3,ICS_PGx2,ICS_PGx1) #pragma config PWP = OFF //Program Flash Write Protect: #pragma config BWP = OFF //Boot Flash Write Protect bit: #pragma config CP = OFF //Code Protect: // //Define function // void Demo01(void); void DSP7SEG( unsigned char *, unsigned int, unsigned int ); void DSP7SEG_i(unsigned int, unsigned int, unsigned int); void InitADC(void); void Get_adc_data(unsigned int *); unsigned int SetIND(unsigned int ); unsigned char SetFNT(unsigned char); void Wait_1mS(unsigned int); void Init_Timer2(void); // //Define parameter // volatile unsigned int G_DISP_int; // 32bit int main(void) { // ******************* // 1.Initialize // ******************* // (1)Define PortB TRISB = 0x00000000; // 32bit LATB = 0x00000000; // 32bit PORTB = 0x00000000; // 32bit // (2)Initialized A/D Converter InitADC(); // (3)Initialized Timer2 Init_Timer2(); // (4)Demo Demo01(); // ******************* // 2.Program Main // ******************* while(1){ DSP7SEG_i(G_DISP_int,100, 3 ); } } //****************************************************************************************** // Function Name : Demo01 // Title : // Input : // Output : //****************************************************************************************** void Demo01(void) { unsigned char demo_str_1[] = {'P','i','c',' '}; unsigned char demo_str_2[] = {'-','-','3','2'}; DSP7SEG(demo_str_1, 2000, 9); DSP7SEG(demo_str_2, 2000, 9); } //****************************************************************************************** // Function Name : DSP7SEG_i // Title : // Input : data, n[mS] , comma(0-3,9[nodisplay]) // Output : // Description : //****************************************************************************************** void DSP7SEG_i(unsigned int int_data, unsigned int disp_time, unsigned int clm) { unsigned char tmp_data_s[5]; sprintf(tmp_data_s,"%4.4d",int_data); DSP7SEG(tmp_data_s, disp_time, clm); } //****************************************************************************************** // Function Name : DSP7SEG // Title : // Input : data, n[mS] , comma(0-3,9[nodisplay]) // Output : // Description : //****************************************************************************************** void DSP7SEG(unsigned char disp_char[], unsigned int disp_time, unsigned int clm) { unsigned int lp,lp_1; unsigned int time_lp; unsigned int tmp_clm; // *************** // 1.Initialize // *************** time_lp = disp_time / 4; tmp_clm = 3 - clm; // *************** // 2.Display // *************** for(lp_1=0;lp_1: Data Output Format bits // 011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) // 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) // 001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) // 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) // 111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) // 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) // 101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) // 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) // AD1CON1[7-5] SSRC<2:0>: Conversion Trigger Source Select bits // 111 = Internal counter ends sampling and starts conversion (auto convert) // 110 = Reserved // 101 = Reserved // 100 = Reserved // 011 = CTMU ends sampling and starts conversion // 010 = Timer 3 period match ends sampling and starts conversion // 001 = Active transition on INT0 pin ends sampling and starts conversion // 000 = Clearing SAMP bit ends sampling and starts conversion // AD1CON1[4] CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) // 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the // ADC interrupt is generated. // 0 = Normal operation, buffer contents will be overwritten by the next conversion sequence // AD1CON1[3] Unimplemented: Read as e0f // AD1CON1[2] ASAM: ADC Sample Auto-Start bit // 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set. // 0 = Sampling begins when SAMP bit is set // AD1CON1[1] SAMP: ADC Sample Enable bit(2) // 1 = The ADC sample and hold amplifier is sampling // 0 = The ADC sample/hold amplifier is holding // When ASAM = 0, writing e1f to this bit starts sampling. // When SSRC = 000, writing e0f to this bit will end sampling and start conversion. // AD1CON1[0] DONE: Analog-to-Digital Conversion Status bit(3) // 1 = Analog-to-digital conversion is done // 0 = Analog-to-digital conversion is not done or has not started // Clearing this bit will not affect any operation in progress. // ******************************* AD1CON1bits.ON = 1; AD1CON1bits.SIDL = 0; AD1CON1bits.FORM = 0b000; AD1CON1bits.SSRC = 0b111; AD1CON1bits.CLRASAM = 0; AD1CON1bits.ASAM = 0; AD1CON1bits.SAMP = 0; AD1CON1bits.DONE = 0; // ******************************* // 2.AD1CON2: ADC CONTROL REGISTER 2 // AD1CON2[31-16] Unimplemented: Read as e0f // AD1CON2[15-13] VCFG<2:0>: Voltage Reference Configuration bits // VREFH VREFL // 000 AVDD AVss // 001 External VREF+ pin AVSS // 010 AVDD External VREF- pin // 011 External VREF+ pin External VREF- pin // 1xx AVDD AVSS // AD1CON2[12] OFFCAL: Input Offset Calibration Mode Select bit // 1 = Enable Offset Calibration mode // Positive and negative inputs of the sample and hold amplifier are connected to VREFL // 0 = Disable Offset Calibration mode // The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL // AD1CON2[11] Unimplemented: Read as e0f // AD1CON2[10] CSCNA: Input Scan Select bit // 1 = Scan inputs // 0 = Do not scan inputs // AD1CON2[9-8] Unimplemented: Read as e0f // AD1CON2[7] BUFS: Buffer Fill Status bit // Only valid when BUFM = 1. // 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 // 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF // AD1CON2[6] Unimplemented: Read as e0f // AD1CON2[5-2] SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits // 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence // 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence // **** // 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence // 0000 = Interrupts at the completion of conversion for each sample/convert sequence // AD1CON2[1] BUFM: ADC Result Buffer Mode Select bit // 1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8 // 0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0 // AD1CON2[0] ALTS: Alternate Input Sample Mode Select bit // 1 = Uses Sample A input multiplexer settings for first sample, then alternates between Sample B and // Sample A input multiplexer settings for all subsequent samples // 0 = Always use Sample A input multiplexer settings // ******************************* AD1CON2bits.VCFG = 0b000; AD1CON2bits.OFFCAL = 0; AD1CON2bits.CSCNA = 0; AD1CON2bits.BUFS = 0; AD1CON2bits.SMPI = 0b0000; AD1CON2bits.BUFM = 0; AD1CON2bits.ALTS = 0; // ******************************* // 3.AD1CON3: ADC CONTROL REGISTER 3 // AD1CON3[31-16] Unimplemented: Read as e0f // AD1CON3[15] ADRC: ADC Conversion Clock Source bit // 1 = Clock derived from FRC // 0 = Clock derived from Peripheral Bus Clock (PBCLK) // AD1CON3[14-13] Unimplemented: Read as e0f // AD1CON3[12-8] SAMC<4:0>: Auto-Sample Time bits(1) // 11111 = 31 TAD // * // * // * // 00001 =1 TAD // 00000 =0 TAD (Not allowed) // AD1CON3[7-0] ADCS<7:0>: ADC Conversion Clock Select bits(2) //@@@@@11111111 =TPBEE2E(ADCS<7:0> + 1) = 512ETPB = TAD // * // * // * // 00000001 =TPBE2E(ADCS<7:0> + 1) = 4ETPB = TAD // 00000000 =TPBE2E(ADCS<7:0> + 1) = 2ETPB = TAD // ******************************* AD1CON3bits.ADRC = 1; AD1CON3bits.SAMC = 0b11111; AD1CON3bits.ADCS = 0b11111111; // ******************************* // 4.AD1CHS: ADC INPUT SELECT REGISTER // AD1CHS[31] CH0NB: Negative Input Select bit for Sample B // 1 = Channel 0 negative input is AN1 // 0 = Channel 0 negative input is VREFL // AD1CHS[30-28] Unimplemented: Read as e0f // AD1CHS[27-24] CH0SB<3:0>: Positive Input Select bits for Sample B // 1111 = Channel 0 positive input is Open(1) // 1110 = Channel 0 positive input is IVREF(2) // 1101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(3) // 1100 = Channel 0 positive input is AN12(4) // E // E // E // 0001 = Channel 0 positive input is AN1 // 0000 = Channel 0 positive input is AN0 // AD1CHS[23] CH0NA: Negative Input Select bit for Sample A Multiplexer Setting(2) // 1 = Channel 0 negative input is AN1 // 0 = Channel 0 negative input is VREFL // AD1CHS[22-20] Unimplemented: Read as e0f // AD1CHS[19-16] CH0SA<3:0>: Positive Input Select bits for Sample A Multiplexer Setting // 1111 = Channel 0 positive input is Open(1) // 1110 = Channel 0 positive input is IVREF(2) // 1101 = Channel 0 positive input is CTMU temperature (CTMUT)(3) // 1100 = Channel 0 positive input is AN12(4) // E // E // E // 0001 = Channel 0 positive input is AN1 // 0000 = Channel 0 positive input is AN0 // AD1CHS[15-0] Unimplemented: Read as e0f // ******************************* AD1CHSbits.CH0NB = 0; AD1CHSbits.CH0SB = 0b0000; AD1CHSbits.CH0NA = 0; AD1CHSbits.CH0SA = 0b0000; // ******************************* // 5.AD1CSSL: ADC INPUT SCAN SELECT REGISTER // AD1CSSL[31-16] Unimplemented: Read as e0f // AD1CSSL[15-0] CSSL<15:0>: ADC Input Pin Scan Selection bits(1,2) // 1 = Select ANx for input scan // 0 = Skip ANx for input scan // Note 1: CSSL = ANx, where x = 0-12; CSSL13 selects CTMU input for scan; CSSL14 selects IVREF for scan; // CSSL15 selects VSS for scan. // 2: On devices with less than 13 analog inputs, all CSSLx bits can be selected; however, inputs selected for // scan without a corresponding input on the device will convert to VREFL. // ******************************* AD1CSSLbits.CSSL0 = 0; AD1CSSLbits.CSSL1 = 0; AD1CSSLbits.CSSL2 = 0; AD1CSSLbits.CSSL3 = 0; AD1CSSLbits.CSSL4 = 0; AD1CSSLbits.CSSL5 = 0; AD1CSSLbits.CSSL6 = 0; AD1CSSLbits.CSSL7 = 0; AD1CSSLbits.CSSL8 = 0; AD1CSSLbits.CSSL9 = 0; AD1CSSLbits.CSSL10 = 0; AD1CSSLbits.CSSL11 = 0; AD1CSSLbits.CSSL12 = 0; AD1CSSLbits.CSSL13 = 0; AD1CSSLbits.CSSL14 = 0; AD1CSSLbits.CSSL15 = 0; } //****************************************************************************************** // Function Name : Get_adc_data // Title : Get A/D-Converter-Data // Input : // Output : //****************************************************************************************** void Get_adc_data(unsigned int *adc_data) { AD1CON1bits.SAMP=1; while(!IFS0bits.AD1IF); *adc_data = (unsigned int)ADC1BUF0 * 3300 / 1023 ; } //****************************************************************************************** // Function Name : Wait_1mS // Title : Wait 1[mS] * n // Input : // Output : // Description : 40MHz, Timer_4 //****************************************************************************************** void Wait_1mS(unsigned int no) { unsigned int lp; // *********************************************** // 1.Define T4CON Register (32Bit) // T4CON(31-16) Unimplemented: Read as e0f // T4CON(15) ON: Timerx On bit // 1 = Starts / 0 = Stop // T4CON(14) Unimplemented: Read as e0f // T4CON(13) SIDL: Stop in Idle Mode bit // 1 = Discontinue module operation when device enters Idle mode // 0 = Continue module operation in Idle mode // T4CON(12-8) Unimplemented: Read as e0f // T4CON(7) TGATE: Timer Gated Time Accumulation Enable bit(3) // When TCS = 1: // This bit is ignored and is read as e0f. // When TCS = 0: // 1 = Gated time accumulation is enabled // 0 = Gated time accumulation is disabled // T4CON(6-4) TCKPS1:TCKPS0: Timerx Input Clock Prescale Select bits // 111 = 1:256 prescale value // 110 = 1:64 prescale value // 101 = 1:32 prescale value // 100 = 1:16 prescale value // 011 = 1:8 prescale value // 010 = 1:4 prescale value // 001 = 1:2 prescale value // 000 = 1:1 prescale value // T4CON(3) T32: 32-Bit Timer Mode Select bit(1) // 1 = Odd numbered and even numbered timers form a 32-bit timer // 0 = Odd numbered and even numbered timers form a separate 16-bit timer // T4CON(2) Unimplemented: Read as e0f // T4CON(1) TCS: Timerx Clock Source Select bit(2) // 1 = External clock from TxCK pin // 0 = Internal peripheral clock // T4CON(0) Unimplemented: Read as e0f // *********************************************** // T4CON = 0b00000000000000001000000001100000; // 1/64,16Bit T4CON = 0b00000000000000001000000000000000; // 1/1, 16Bit // *********************************************** // 2.Set PR4-Register (PR2[31-16]:Unimplemented, PR2[15-0]timer ) // *********************************************** // PR4 = 0x00003D09; //10Hz (0x3D09;0d15625) // FRC 40MHz 40MHz/1(pic32)/256(prescale)/10(Hz) // PR4 = 0x00004C4B; // 8Hz (0x9896;0d19531.25) // FRC 40MHz 40MHz/1(pic32)/256(prescale)/8(Hz) // PR4 = 0x00009896; // 4Hz (0x9896;0d39062.5) // FRC 40MHz 40MHz/1(pic32)/256(prescale)/4(Hz) // PR4 = 0x00007A12; // 1Hz (0x7A12;0d31250) // FRC 8MHz 8MHz/1(pic32)/256(prescale)/1(Hz) // PR4 = 0x0000186A; // 5Hz (0x186A;0d6250) // FRC 8MHz 8MHz/1(pic32)/256(prescale)/5(Hz) // PR4 = 0x00000FA0; //10KHz(0x0FA0;0d4000) // FRC 40MHz 40MHz/1(pic32)/1(prescale) /10000(Hz) PR4 = 0x00009C40; // 1KHz(0x9C40;0d40000) // FRC 40MHz 40MHz/1(pic32)/1(prescale) /1000(Hz) // *********************************************** // 3.Timer // *********************************************** for(lp=0;lp