;****************************************************************************************** ; PIC18F14K50 Sample Program ; Project : ; Program Name : ; Programer : ; Create date : Version 1.0 H22.08.20 ; History : ; Laungage : MPLAB MPASM ;****************************************************************************************** ; (1)Description ; ;****************************************************************************************** LIST P=PIC18F14K50,ST=OFF,R=DEC INCLUDE "P18F14K50.inc" config CPUDIV = NOCLKDIV ;CPU System Clock Selection bit(No CPU System Clock divide) config USBDIV = OFF ;USB Clock Selection bit(USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide) ; config FOSC = HS ;Oscillator Selection bits(HS oscillator) config FOSC = IRC ;Oscillator Selection bits(Internal RC oscillator) config PLLEN = ON ;X PLL Enable bit(Oscillator multiplied by 4) config PCLKEN = OFF ;Primary Clock Enable Bit(Primary clock is under software control) config FCMEN = OFF config IESO = OFF ;Internal/External Oscillator Switchover bit(Oscillator Switchover mode disabled) config PWRTEN = OFF,BOREN = OFF,BORV = 19 config WDTEN = OFF,WDTPS = 1 config MCLRE = OFF ;MCLR Pin Enable bit(RE3 input pin enabled; MCLR disabled) config HFOFST = OFF,STVREN = OFF,LVP = OFF,BBSIZ = OFF,XINST = OFF config CP0 = OFF,CP1 = OFF,CPB = OFF,CPD = OFF,WRT0 = OFF,WRT1 = OFF,WRTB = OFF,WRTC = OFF,WRTD = OFF,EBTR0 = OFF,EBTR1 = OFF,EBTRB = OFF TMP_C EQU 00H TMP_C1 EQU 01H IEEADR_L EQU 02H IEEADR_H EQU 03H EEDAT EQU 04H LP0 EQU 05H LP1 EQU 06H LP2 EQU 07H ORG 0h GOTO START ORG 8h GOTO START ORG 18h GOTO START START ; ***************************** ; 1.Initialized Segment ; ***************************** ; (1)Initialize oscillator CALL INTOSC ; (2)Define I/O port MOVLW H'FF' MOVWF TRISA MOVLW H'FF' MOVWF TRISB MOVLW H'FF' MOVWF TRISC ; (3)Initialize EUSAR CALL INTUART ; ***************************** ; 2.Program main ; ***************************** ; (1)Send Message CALL DEMO01 ; (2)Main loop MAIN CALL DEMO_INTEEP GOTO MAIN ;****************************************************************************************** ; Program : DEMO01 ; Title : ; Input : ; Output : ;****************************************************************************************** DEMO01 MOVLW ' ' CALL SNDUART MOVLW 'P' CALL SNDUART MOVLW 'I' CALL SNDUART MOVLW 'C' CALL SNDUART MOVLW '1' CALL SNDUART MOVLW '8' CALL SNDUART MOVLW 'F' CALL SNDUART MOVLW '1' CALL SNDUART MOVLW '4' CALL SNDUART MOVLW 'K' CALL SNDUART MOVLW '5' CALL SNDUART MOVLW '0' CALL SNDUART MOVLW ' ' CALL SNDUART MOVLW 'C' CALL SNDUART MOVLW 'o' CALL SNDUART MOVLW 'n' CALL SNDUART MOVLW 'n' CALL SNDUART MOVLW 'e' CALL SNDUART MOVLW 'c' CALL SNDUART MOVLW 't' CALL SNDUART MOVLW 'e' CALL SNDUART MOVLW 'd' CALL SNDUART MOVLW ' ' CALL SNDUART MOVLW 'O' CALL SNDUART MOVLW 'K' CALL SNDUART MOVLW '>' CALL SNDUART MOVLW ' ' CALL SNDUART RETURN ;****************************************************************************************** ; Program : DEMO_INTEEP ; Title : Internal Data EEP-ROM Memory ; Input : ; Output : ;****************************************************************************************** DEMO_INTEEP ; ******************************** ; 1.Write Internal Data EEP-ROM Memory ; ******************************** MOVLW H'00' MOVWF IEEADR_H MOVLW H'00' MOVWF IEEADR_L CALL RECUART MOVWF TMP_C1 CALL SNDUART MOVF TMP_C1,W CALL WRTINTEEP ; MOVLW H'00' MOVWF IEEADR_H MOVLW H'01' MOVWF IEEADR_L CALL RECUART MOVWF TMP_C1 CALL SNDUART MOVF TMP_C1,W CALL WRTINTEEP ; MOVLW H'00' MOVWF IEEADR_H MOVLW H'02' MOVWF IEEADR_L CALL RECUART MOVWF TMP_C1 CALL SNDUART MOVF TMP_C1,W CALL WRTINTEEP ; MOVLW H'00' MOVWF IEEADR_H MOVLW H'03' MOVWF IEEADR_L CALL RECUART MOVWF TMP_C1 CALL SNDUART MOVF TMP_C1,W CALL WRTINTEEP ; MOVLW H'00' MOVWF IEEADR_H MOVLW H'04' MOVWF IEEADR_L CALL RECUART MOVWF TMP_C1 CALL SNDUART MOVF TMP_C1,W CALL WRTINTEEP ; ; ; ******************************** ; 1.Read Internal Data EEP-ROM Memory ; ******************************** CLRF EEDATA CLRF EEDAT MOVLW '[' CALL SNDUART MOVLW H'00' MOVWF IEEADR_H MOVLW H'00' MOVWF IEEADR_L CALL REDINTEEP CALL SNDUART ; MOVLW H'00' MOVWF IEEADR_H MOVLW H'01' MOVWF IEEADR_L CALL REDINTEEP CALL SNDUART ; MOVLW H'00' MOVWF IEEADR_H MOVLW H'02' MOVWF IEEADR_L CALL REDINTEEP CALL SNDUART ; MOVLW H'00' MOVWF IEEADR_H MOVLW H'03' MOVWF IEEADR_L CALL REDINTEEP CALL SNDUART ; MOVLW H'00' MOVWF IEEADR_H MOVLW H'04' MOVWF IEEADR_L CALL REDINTEEP CALL SNDUART ; MOVLW ']' CALL SNDUART RETURN ;****************************************************************************************** ; Function Name : INTOSC ; Title : Initialize oscillator ; Input : ; Output : ; Description : Internal oscillator 16MHz ;****************************************************************************************** INTOSC ; ******************************************************* ; 1.Define OSCCON(OSCILLATOR CONTROL REGISTER) ; OSCCON(7) IDLEN: Idle Enable bit ; 1 = Device enters Idle mode on SLEEP instruction ; 0 = Device enters Sleep mode on SLEEP instruction ; OSCCON(6-4) IRCF<2:0>: Internal Oscillator Frequency Select bits ; 111 = 16 MHz ; 110 = 8 MHz ; 101 = 4 MHz ; 100 = 2 MHz ; 011 = 1 MHz(3) ; 010 = 500 kHz ; 001 = 250 kHz ; 000 = 31 kHz(2) ; OSCCON(3) OSTS: Oscillator Start-up Time-out Status bit(1) ; 1 = Device is running from the clock defined by FOSC<2:0> of the CONFIG1 register ; 0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC) ; OSCCON(2) HFIOFS: HFINTOSC Frequency Stable bit ; 1 = HFINTOSC frequency is stable ; 0 = HFINTOSC frequency is not stable ; OSCCON(1-0) SCS<1:0>: System Clock Select bits ; 1x = Internal oscillator block ; 01 = Secondary (Timer1) oscillator ; 00 = Primary clock (determined by CONFIG1H[FOSC<3:0>]). ; ******************************************************* MOVLW B'11111111' ;Internal 16MHz MOVWF OSCCON ; ******************************************************* ; 2.Define OSCCON2(OSCILLATOR CONTROL REGISTER 2) ; OSCCON2(7-3) Unimplemented: Read as ‘0’ ; OSCCON2(2) PRI_SD: Primary Oscillator Drive Circuit shutdown bit ; 1 = Oscillator drive circuit on ; 0 = Oscillator drive circuit off (zero power) ; OSCCON2(1) HFIOFL: HFINTOSC Frequency Locked bit ; 1 = HFINTOSC is in lock ; 0 = HFINTOSC has not yet locked ; OSCCON2(0) LFIOFS: LFINTOSC Frequency Stable bit ; 1 = LFINTOSC is stable ; 0 = LFINTOSC is not stable ; ******************************************************* MOVLW B'00000000' MOVWF OSCCON2 ; ******************************************************* ; 3.Define OSCTUNE(OSCILLATOR TUNING REGISTER) ; OSCTUNE(7) INTSRC: Internal Oscillator Low-Frequency Source Select bit ; 1 = 31.25 kHz device clock derived from 16 MHz HFINTOSC source (divide-by-512 enabled) ; 0 = 31 kHz device clock derived directly from LFINTOSC internal oscillator ; OSCTUNE(6) SPLLEN: Software Controlled Frequency Multiplier PLL bit ; 1 = PLL enabled (for HFINTOSC 8 MHz only) ; 0 = PLL disabled ; OSCTUNE(5-0) TUN<5:0>: Frequency Tuning bits ; 011111 = Maximum frequency ; 011110 = ; ・・・・ ; 000001 = ; 000000 = Oscillator module is running at the factory calibrated frequency. ; 111111 = ; ・・・・ ; 100000 = Minimum frequency ; ******************************************************* MOVLW B'00000000' MOVWF OSCTUNE RETURN ;****************************************************************************************** ; Program : INTUART ; Title : ; Input : ; Output : ; Description : Fosc:16MHz, Baud Rate:9600BPS, 16-bit Baud Rate ;****************************************************************************************** INTUART ; ******************************************************* ; 0.Define ANSELH(ANALOG SELECT REGISTER 2) ; ANSELH(3) ANS11: RB5 Analog Select Control bit ; 0 = Digital input buffer of RB5 is enabled ; ******************************************************* BCF ANSELH,ANS11 ; ******************************************************* ; 1.Define TXSTA(TRANSMIT STATUS AND CONTROL) Register ; TXSTA(7) CSRC: Clock Source Select bit ; Asynchronous mode:Don’t care ; TXSTA(6) TX9: 9-bit Transmit Enable bit ; 1 = Selects 9-bit transmission ; 0 = Selects 8-bit transmission ; TXSTA(5) TXEN: Transmit Enable bit(1) ; 1 = Transmit enabled ; 0 = Transmit disabled ; TXSTA(4) SYNC: EUSART Mode Select bit ; 1 = Synchronous mode ; 0 = Asynchronous mode ; TXSTA(3) SENDB: Send Break Character bit ; Asynchronous mode: ; 1 = Send Sync Break on next transmission (cleared by hardware upon completion) ; 0 = Sync Break transmission completed ; TXSTA(2) BRGH: High Baud Rate Select bit ; Asynchronous mode: ; 1 = High speed ; 0 = Low speed ; TXSTA(1) TRMT: Transmit Shift Register Status bit ; 1 = TSR empty ; 0 = TSR full ; TXSTA(0) TX9D: Ninth bit of Transmit Data ; Can be address/data bit or a parity bit. ; ******************************************************* MOVLW B'00100100' MOVWF TXSTA ; ******************************************************* ; 2.Define RCSTA(RECEIVE STATUS AND CONTROL) Register ; RCSTA(7) SPEN: Serial Port Enable bit ; 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) ; 0 = Serial port disabled (held in Reset) ; RCSTA(6) RX9: 9-bit Receive Enable bit ; 1 = Selects 9-bit reception ; 0 = Selects 8-bit reception ; RCSTA(5) SREN: Single Receive Enable bit ; Asynchronous mode: ; Don’t care ; RCSTA(4) CREN: Continuous Receive Enable bit ; Asynchronous mode: ; 1 = Enables receiver ; 0 = Disables receiver ; RCSTA(3) ADDEN: Address Detect Enable bit ; Asynchronous mode 9-bit (RX9 = 1): ; 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set ; 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit ; Asynchronous mode 8-bit (RX9 = 0): ; Don’t care ; RCSTA(2) FERR: Framing Error bit ; 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) ; 0 = No framing error ; RCSTA(1) OERR: Overrun Error bit ; 1 = Overrun error (can be cleared by clearing bit CREN) ; 0 = No overrun error ; RCSTA(0) RX9D: Ninth bit of Received Data ; This can be address/data bit or a parity bit and must be calculated by user firmware. ; ******************************************************* MOVLW B'10010000' MOVWF RCSTA ; ******************************************************* ; 3.Define BAUDCON(BAUD RATE CONTROL) Register ; BAUDCON(7) ABDOVF: Auto-Baud Detect Overflow bit ; Asynchronous mode: ; 1 = Auto-baud timer overflowed ; 0 = Auto-baud timer did not overflow ; BAUDCON(6) RCIDL: Receive Idle Flag bit ; Asynchronous mode: ; 1 = Receiver is Idle ; 0 = Start bit has been detected and the receiver is active ; BAUDCON(5) DTRXP: Data/Receive Polarity Select bit ; Asynchronous mode: ; 1 = Receive data (RX) is inverted (active-low) ; 0 = Receive data (RX) is not inverted (active-high) ; BAUDCON(4) CKTXP: Clock/Transmit Polarity Select bit ; Asynchronous mode: ; 1 = Idle state for transmit (TX) is low ; 0 = Idle state for transmit (TX) is high ; BAUDCON(3) BRG16: 16-bit Baud Rate Generator bit ; 1 = 16-bit Baud Rate Generator is used (SPBRGH:SPBRG) ; 0 = 8-bit Baud Rate Generator is used (SPBRG) ; BAUDCON(2) Unimplemented: Read as ‘0’ ; BAUDCON(1) WUE: Wake-up Enable bit ; Asynchronous mode: ; 1 = Receiver is waiting for a falling edge. No character will be received but RCIF will be set on ; the falling edge. WUE will automatically clear on the rising edge. ; 0 = Receiver is operating normally ; BAUDCON(0) ABDEN: Auto-Baud Detect Enable bit ; Asynchronous mode: ; 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) ; 0 = Auto-Baud Detect mode is disabled ; ******************************************************* MOVLW B'00001000' MOVWF BAUDCON ; ******************************************************* ; 3.Define BRG(EUSART Baud Rate Generator Register) Register ; ******************************************************* ; BRG = 48000000(Hz)/4/9600(BPS)-1 ==> 0d1249 ==> 0x4E1 ; BRG = 16000000(Hz)/4/9600(BPS)-1 ==> 0d0416 ==> 0x1A0 ; BRG = 16000000(Hz)/4/19200(BPS)-1 ==> 0d0207 ==> 0x0CF ; (1)Define SPBRGH(EUSART Baud Rate Generator Register, High Byte) Register MOVLW H'01' MOVWF SPBRGH ; (2)Define SPBRG(EUSART Baud Rate Generator Register, Low Byte) Register MOVLW H'A0' MOVWF SPBRG RETURN ;****************************************************************************************** ; Program : RECUART ; Title : ; Input : ; Output : ;****************************************************************************************** RECUART ; **************************** ; 1.Check Recvive Flag ; **************************** BCF PIR1,RCIF RECUART_1 BTFSS PIR1,RCIF GOTO RECUART_1 ; **************************** ; 2.Check error ; **************************** BTFSS RCSTA,FERR GOTO RECUART_2 MOVLW H'00' RETURN RECUART_2 BTFSS RCSTA,OERR GOTO RECUART_3 MOVLW H'00' RETURN RECUART_3 ; **************************** ; 3.Set Recive Data ; **************************** MOVF RCREG,W RETURN ;****************************************************************************************** ; Program : SNDUART ; Title : ; Input : ; Output : ;****************************************************************************************** SNDUART MOVWF TMP_C ; *************************** ; 1.Check Send Flag ; *************************** SNDUART_1 BTFSS TXSTA,TRMT GOTO SNDUART_1 ; *************************** ; 2.Set data ; *************************** MOVF TMP_C,W MOVWF TXREG RETURN ;****************************************************************************************** ; Program : WRTINTEEP ; Title : Write Internal Data EEP-ROM Memory ; Input : IEEADR_L,IEEADR_H,W-reg(EEDAT) ; Output : ;****************************************************************************************** WRTINTEEP MOVWF EEDAT MOVF IEEADR_L,W MOVWF EEADR ; Data Memory Address to write MOVF IEEADR_H,W MOVWF EEADRH MOVF EEDAT,W MOVWF EEDATA ; Data Memory Value to write ; BCF EECON1,EEPGD ; Point to DATA memory BCF EECON1,CFGS ; Access EEPROM BSF EECON1,WREN ; Enable writes BCF INTCON,GIE ; Disable Interrupts MOVLW 55h MOVWF EECON2 ; Write 55h MOVLW 0AAh MOVWF EECON2 ; Write 0AAh BSF EECON1,WR ; Set WR bit to begin write BSF INTCON,GIE ; Enable Interrupts BCF EECON1,WREN ; Disable writes on write complete (EEIF set) CALL Timer ; RETURN ;****************************************************************************************** ; Program : REDINTEEP ; Title : Read Internal Data EEP-ROM Memory ; Input : IEEADR_L,IEEADR_H ; Output : W-reg(EEDAT) ;****************************************************************************************** REDINTEEP MOVF IEEADR_L,W MOVWF EEADR ; Data Memory Address to read MOVF IEEADR_H,W MOVWF EEADRH BCF EECON1,EEPGD ; Point to DATA memory BCF EECON1,CFGS ; Access EEPROM BSF EECON1,RD ; EEPROM Read MOVF EEDATA,W ; W = EEDATA RETURN ;****************************************************************************************** ; Program : REFINTEEP ; Title : Refresh Internal Data EEP-ROM Memory ; Input : ; Output : ;****************************************************************************************** REFINTEEP CLRF EEADR ; Start at address 0 BCF EECON1,CFGS ; Set for memory BCF EECON1,EEPGD ; Set for Data EEPROM BCF INTCON,GIE ; Disable interrupts BSF EECON1,WREN ; Enable writes REFINTEEP_1 ; Loop to refresh array BSF EECON1,RD ; Read current address MOVLW 55h MOVWF EECON2 ; Write 55h MOVLW 0AAh MOVWF EECON2 ; Write 0AAh BSF EECON1,WR ; Set WR bit to begin write BTFSC EECON1,WR ; Wait for write to complete BRA $-2 INCFSZ EEADR,F ; Increment address BRA REFINTEEP_1 ; Not zero, do it again BCF EECON1,WREN ; Disable writes BSF INTCON,GIE ; Enable interrupts RETURN ;****************************************************************************************** ; Function Name : Timer ; Title : wait function (10mS) ; Input : ; Output : ;****************************************************************************************** Timer: ; ******************************************************* ; 1.Define T1CON(TIMER1 CONTROL REGISTER) Register ; T1CON(7) RD16: 16-bit Read/Write Mode Enable bit ; 1 = Enables register read/write of TImer1 in one 16-bit operation ; 0 = Enables register read/write of Timer1 in two 8-bit operations ; T1CON(6) T1RUN: Timer1 System Clock Status bit ; 1 = Main system clock is derived from Timer1 oscillator ; 0 = Main system clock is derived from another source ; T1CON(5-4)T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits ; 11 = 1:8 Prescale value ; 10 = 1:4 Prescale value ; 01 = 1:2 Prescale value ; 00 = 1:1 Prescale value ; T1CON(3) T1OSCEN: Timer1 Oscillator Enable bit ; 1 = Timer1 oscillator is enabled ; 0 = Timer1 oscillator is shut off ; The oscillator inverter and feedback resistor are turned off to eliminate power drain. ; T1CON(2) T1SYNC: Timer1 External Clock Input Synchronization Select bit ; When TMR1CS = 1: ; 1 = Do not synchronize external clock input ; 0 = Synchronize external clock input ; When TMR1CS = 0: ; This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. ; T1CON(1) TMR1CS: Timer1 Clock Source Select bit ; 1 = External clock from the T13CKI pin (on the rising edge) ; 0 = Internal clock (FOSC/4) ; T1CON(0) bit 0 TMR1ON: Timer1 On bit ; 1 = Enables Timer1 ; 0 = Stops Timer1 ; ******************************************************* MOVLW B'10110001' ; 16-bit Read/Write Mode, 1:8 Prescale value MOVWF T1CON ; ******************************************************* ; 2.Define TMR1 Register ; Caution(16-bit Read/Write Mode) !!!!: ; (a)Writing to TMR1H does not directly affect Timer1. ; Instead, the high byte of Timer1 is updated with the contents of TMR1H when a write occurs to TMR1L. ; This allows all 16 bits of Timer1 to be updated at once. ; (b)A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. ; This provides the user with the ability to accurately read all 16 bits of Timer1 without the need to ; determine whether a read of the high byte, followed by a read of the low byte, has become invalid due ; to a rollover or carry between reads. ; ******************************************************* ; TMR1 data ( OSC:12MHz, 4X PLLON, 1:8 Prescale value, 0.01[S];100Hz ) ; 10mS(100Hz): 12MHz * 4(PLLON) / 4(PIC) / 8(Prescale) / 100(100Hz)==> 0d15,000(Count) ==> 0x3A98(Count) ; TMR1 = 0xFFFF - 0x3A98 ==> 0xC567 ; TMR1 data ( Internal OSC:16MHz, 1:8 Prescale value, 0.01[S];100Hz ) ; 10mS(100Hz): 16MHz / 4(PIC) / 8(Prescale) / 100(100Hz)==> 0d5,000(Count) ==> 0x1388(Count) ; TMR1 = 0xFFFF - 0x1388 ==> 0xEC77 MOVLW H'EC' MOVWF TMR1H MOVLW H'77' MOVWF TMR1L ; ******************************************************* ; 3.Timer ; ******************************************************* BCF PIR1,TMR1IF Timer_1 BTFSS PIR1,TMR1IF GOTO Timer_1 RETURN END