;****************************************************************************************** ; PIC12F1501 Sample Program : This sample program make the DAC output ; Project : ; Program Name : ; Programer : ; Create date : Version 1.0 H26.04.10 ; History : ; Laungage : MPLAB MPASM ; ;****************************************************************************************** ; Description ; OSC : Internal OSC 16MHz ; Assign I/O pins ; Ra0[O] : DACOUT1 ; Ra2[O] : DACOUT2 ;****************************************************************************************** LIST P=PIC12F1501,ST=OFF,R=DEC INCLUDE "P12F1501.inc" __CONFIG _CONFIG1 , _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _BOREN_OFF & _CLKOUTEN_OFF __CONFIG _CONFIG2 , _WRT_OFF & _STVREN_OFF & _BORV_HI & _LPBOR_OFF & _LVP_OFF ; ; Define GENERAL PURPOSE RAM AREA (80 bytes maximum) 20h-6fh ; TMP_G EQU 20H ; ; Define Common RAM AREA (16 bytes) 70h-7fh ; TMP_C EQU 70H ; ; Define Macro ; SELBANK MACRO #BANK_NO MOVLW #BANK_NO MOVWF BSR ; The active bank is selected by writing the bank number into the Bank Select Register (BSR) ENDM SETDAC MACRO #DAC_DATA ; 0 <= DAC_DATA <= 31 MOVLW #DAC_DATA MOVWF DACCON1 CALL WAIT_05MS SELBANK 2 ENDM ; ; Program Start ; ORG 0h GOTO START ORG 4h GOTO START START ; ***************************** ; 1.Initialized ; ***************************** ; (1)Define OSC (16MHz, IntOSC) SELBANK 1 ; SET BANK1 MOVLW B'01111010' MOVWF OSCCON ; (2)Define ANSELA Register ; The ANSELA register is used to configure the Input mode of an I/O pin to analog. SELBANK 3 CLRF ANSELA ; All Degital Port ; (3)Define I/O port SELBANK 1 ; SET BANK1 MOVLW B'11111111' MOVWF TRISA ; (4)Initialized DAC CALL INITDAC ; ***************************** ; 2.Program main ; ***************************** SELBANK 2 ; (1)Main loop MAIN SETDAC 15 SETDAC 17 SETDAC 20 SETDAC 22 SETDAC 24 SETDAC 26 SETDAC 27 SETDAC 28 SETDAC 29 SETDAC 30 SETDAC 30 SETDAC 30 SETDAC 29 SETDAC 28 SETDAC 27 SETDAC 26 SETDAC 24 SETDAC 22 SETDAC 20 SETDAC 17 SETDAC 15 SETDAC 13 SETDAC 10 SETDAC 8 SETDAC 6 SETDAC 4 SETDAC 3 SETDAC 2 SETDAC 1 SETDAC 0 SETDAC 0 SETDAC 0 SETDAC 1 SETDAC 2 SETDAC 3 SETDAC 4 SETDAC 6 SETDAC 8 SETDAC 10 SETDAC 13 GOTO MAIN ;****************************************************************************************** ; Program : INITDAC ; Title : ; Input : ; Output : ;****************************************************************************************** INITDAC ; ******************************************************* ; 1.Define FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER ; FVRCON[7] FVREN: Fixed Voltage Reference Enable bit ; 1 = Fixed Voltage Reference is enabled / 0 = Fixed Voltage Reference is disabled ; FVRCON[6] FVRRDY: Fixed Voltage Reference Ready Flag bit ; 1 = Fixed Voltage Reference output is ready for use / 0 = Fixed Voltage Reference output is not ready or not enabled ; FVRCON[5] TSEN: Temperature Indicator Enable bit ; 1 = Temperature Indicator is enabled / 0 = Temperature Indicator is disabled ; FVRCON[4] TSRNG: Temperature Indicator Range Selection bit ; 1 = VOUT = VDD - 4VT (High Range) ; 0 = VOUT = VDD - 2VT (Low Range) ; FVRCON[3-2] CDAFVR<1:0>: Comparator Fixed Voltage Reference Selection bits ; 11 = Comparator Fixed Voltage Reference Peripheral output is 4x (4.096V) ; 10 = Comparator Fixed Voltage Reference Peripheral output is 2x (2.048V) ; 01 = Comparator Fixed Voltage Reference Peripheral output is 1x (1.024V) ; 00 = Comparator Fixed Voltage Reference Peripheral output is off ; FVRCON[1-0] ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit ; 11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V) ; 10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V) ; 01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V) ; 00 = ADC Fixed Voltage Reference Peripheral output is off ; ******************************************************* ; SELBANK 2 ; MOVLW B'00000000' ; MOVWF FVRCON ; ******************************************************* ; 2.Define DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0 ; DACCON0[7] DACEN: DAC Enable bit ; 1 = DAC is enabled / 0 = DAC is disabled ; DACCON0[6] Unimplemented: Read as e0f ; DACCON0[5] DACOE1: DAC Voltage Output Enable bit ; 1 = DAC voltage level is also an output on the DACOUT1 pin ; 0 = DAC voltage level is disconnected from the DACOUT1 pin ; DACCON0[4] DACOE2: DAC Voltage Output Enable bit ; 1 = DAC voltage level is also an output on the DACOUT2 pin ; 0 = DAC voltage level is disconnected from the DACOUT2 pin ; DACCON0[3] Unimplemented: Read as e0f ; DACCON0[2] DACPSS: DAC Positive Source Select bit ; 1 = VREF+ pin ; 0 = VDD ; DACCON0[1-0] Unimplemented: Read as e0f ; ******************************************************* SELBANK 2 MOVLW B'10110000' MOVWF DACCON0 ; ******************************************************* ; 3.Define DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1 ; DACCON1[7-5] Unimplemented: Read as e0f ; DACCON1[4-0] DACR<4:0>: DAC Voltage Output Select bits ; ******************************************************* SELBANK 2 MOVLW B'00000000' MOVWF DACCON1 SELBANK 0 ; SET BANK0 RETURN ;****************************************************************************************** ; Function Name : Wait_05mS ; Title : This function will wait 0.5 mS ; Input : ; Output : ;****************************************************************************************** WAIT_05MS ; ******************************************************* ; 1.Define T1CON(TIMER1 CONTROL REGISTER) Register ; T1CON(7-6) TMR1CS<1:0>: Timer1 Clock Source Select bits ; 11 =Timer1 clock source is LFINTOSC ; 10 =Timer1 clock source is T1CKI pin (on rising edge) ; 01 =Timer1 clock source is system clock (FOSC) ; 00 =Timer1 clock source is instruction clock (FOSC/4) ; T1CON(5-4) T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits ; 11 = 1:8 Prescale value ; 10 = 1:4 Prescale value ; 01 = 1:2 Prescale value ; 00 = 1:1 Prescale value ; T1CON(3) Unimplemented: Read as e0f ; T1CON(2) T1SYNC: Timer1 Synchronization Control bit ; 1 = Do not synchronize asynchronous clock input ; 0 = Synchronize asynchronous clock input with system clock (FOSC) ; T1CON(1) Unimplemented: Read as e0f ; T1CON(0) TMR1ON: Timer1 On bit ; 1 = Enables Timer1 ; 0 = Stops Timer1 and clears Timer1 gate flip-flop ; ******************************************************* SELBANK 0 ; SET BANK0 MOVLW B'00000001' MOVWF T1CON ; ******************************************************* ; 2.Define T1GCON (TIMER1 GATE CONTROL REGISTER) Register ; T1GCON(7) TMR1GE: Timer1 Gate Enable bit ; If TMR1ON = 0: This bit is ignored ; If TMR1ON = 1: ; 1 = Timer1 counting is controlled by the Timer1 gate function ; 0 = Timer1 counts regardless of Timer1 gate function ; T1GCON(6) T1GPOL: Timer1 Gate Polarity bit ; 1 = Timer1 gate is active-high (Timer1 counts when gate is high) ; 0 = Timer1 gate is active-low (Timer1 counts when gate is low) ; T1GCON(5) T1GTM: Timer1 Gate Toggle Mode bit ; 1 = Timer1 Gate Toggle mode is enabled ; 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared ; T1GCON(4) T1GSPM: Timer1 Gate Single-Pulse Mode bit ; 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate ; 0 = Timer1 Gate Single-Pulse mode is disabled ; T1GCON(3) T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit ; 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge ; 0 = Timer1 gate single-pulse acquisition has completed or has not been started ; T1GCON(2) T1GVAL: Timer1 Gate Current State bit ; Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. ; Unaffected by Timer1 Gate Enable (TMR1GE). ; T1GCON(1-0) T1GSS<1:0>: Timer1 Gate Source Select bits ; 11 = Reserved ; 10 = Comparator 1 optionally synchronized output (sync_C1OUT) ; 01 = Timer0 overflow output ; 00 = Timer1 gate pin ; ******************************************************* MOVLW B'00000000' MOVWF T1GCON ; ******************************************************* ; 3.Define TMR1 Register ; ******************************************************* ; TMR1 data ( OSC:16MHz, FOSC/4, 1:1 Prescale value, 0.0005[S];2000Hz ) ; 0.5mS(2000Hz): 16MHz / 4(FOSC/4) / 1(Prescale) / 2000(2000Hz)==> 0d2,000(Count) ==> 0x07D0(Count) ; TMR1 = 0xFFFF - 0x07D0 ==> 0xF82F ; TMR1 data ( OSC:16MHz, FOSC/4, 1:1 Prescale value, 0.001[S];1000Hz ) ; 1mS(1000Hz): 16MHz / 4(FOSC/4) / 1(Prescale) / 1000(1000Hz)==> 0d4,000(Count) ==> 0x0FA0(Count) ; TMR1 = 0xFFFF - 0x0FA0 ==> 0xF05F ; TMR1 data ( OSC:16MHz, FOSC/4, 1:8 Prescale value, 0.01[S];100Hz ) ; 10mS(100Hz): 16MHz / 4(FOSC/4) / 8(Prescale) / 100(100Hz)==> 0d5,000(Count) ==> 0x1388(Count) ; TMR1 = 0xFFFF - 0x1388 ==> 0xEC77 ; TMR1 data ( OSC:16MHz, FOSC/4, 1:8 Prescale value, 0.1[S];10Hz ) ; 100mS(10Hz): 16MHz / 4(FOSC/4) / 8(Prescale) / 10(10Hz) ==> 0d50,000(Count) ==> 0xC350(Count) ; TMR1 = 0xFFFF - 0xC350 ==> 0x3CAF MOVLW H'F8' MOVWF TMR1H ; MOVLW H'2F' MOVLW H'4A' MOVWF TMR1L ; ******************************************************* ; 4.Timer ; ******************************************************* BCF PIR1,TMR1IF BTFSS PIR1,TMR1IF GOTO $-1 RETURN END