;****************************************************************************************** ; PIC12F1501 Sample Program : ; Project : ; Program Name : ; Programer : ; Create date : Version 1.0 H26.10.01 ; History : ; Laungage : MPLAB MPASM ; ;****************************************************************************************** ; Description ; OSC : Internal OSC 16MHz ; Assign I/O pins ; RA0 : AN0 , Input A/D conveter data ; RA5 : NCO1, Numerically Controlled Oscillator output. ;****************************************************************************************** LIST P=PIC12F1501,ST=OFF,R=DEC INCLUDE "P12F1501.inc" __CONFIG _CONFIG1 , _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _BOREN_OFF & _CLKOUTEN_OFF __CONFIG _CONFIG2 , _WRT_OFF & _STVREN_OFF & _BORV_HI & _LPBOR_OFF & _LVP_OFF ; ; Define GENERAL PURPOSE RAM AREA (80 bytes maximum) 20h-6fh ; TMP_G EQU 20H TMP_G1 EQU 21H TMP_G2 EQU 22H ; ; Define Common RAM AREA (16 bytes) 70h-7fh ; TMP_C EQU 70H ADDAT_H EQU 71H ADDAT_L EQU 72H ; ; Define Macro ; SELBANK MACRO #BANK_NO MOVLW #BANK_NO MOVWF BSR ; The active bank is selected by writing the bank number into the Bank Select Register (BSR) ENDM ; ; Program Start ; ORG 0h GOTO START ORG 4h GOTO START START ; ***************************** ; 1.Initialized ; ***************************** ; (1)Define OSC (16MHz, IntOSC) SELBANK 1 ; SET BANK1 MOVLW B'01111010' MOVWF OSCCON ; (2)Define I/O port SELBANK 1 ; SET BANK1 MOVLW B'11011111' MOVWF TRISA ; (3)Define ANSELA Register ; The ANSELA register is used to configure the Input mode of an I/O pin to analog. SELBANK 3 CLRF ANSELA ; All Degital Port BSF ANSELA,ANSA0 ; Set the analog input AN0 ; (4)Initialized A/D Converter Module CALL INTADC ; (5)Initialized NCO Module CALL INITNCO SELBANK 0 ; ***************************** ; 2.Program main ; ***************************** ; Main loop MAIN ; (1)Get the data from the A/D Converter CALL GETADC ; (2)Set the data to the NCO CALL SETNCO ; (3)Wait for 1 millisecond CALL WAIT_1MS CALL WAIT_1MS CALL WAIT_1MS CALL WAIT_1MS GOTO MAIN ;******************************************************************************************* ; Function Name : INITNCO@@@@ ; Function : Initialize NCO Module ; Input : ; Output : ; Description : ;******************************************************************************************* INITNCO ; **************************************************************** ; 0.APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER ; APFCON[7] CWG1BSEL: Pin Selection bit ; 1 = CWG1B function is on RA4 / 0 = CWG1B function is on RA0 ; APFCON[6] CWG1ASEL: Pin Selection bit ; 1 = CWG1A function is on RA5 / 0 = CWG1A function is on RA2 ; APFCON[5-4] Unimplemented: Read as e0f ; APFCON[3] T1GSEL: Pin Selection bit ; 1 = T1G function is on RA3 / 0 = T1G function is on RA4 ; APFCON[2] Unimplemented: Read as e0f ; APFCON[1] CLC1SEL: Pin Selection bit ; 1 = CLC1 function is on RA4 / 0 = CLC1 function is on RA2 ; APFCON[0] NCO1SEL: Pin Selection bit ; 1 = NCO1 function is on RA5 / 0 = NCO1 function is on RA1 ; **************************************************************** SELBANK 2 MOVLW B'00000001' MOVWF APFCON ; **************************************************************** ; 1.NCOxCON:NCOx CONTROL REGISTER ; NCOxCON[7] NxEN: NCOx Enable bit ; 1 = NCOx module is enabled / 0 = NCOx module is disabled ; NCOxCON[6] NxOE: NCOx Output Enable bit ; 1 = NCOx output pin is enabled / 0 = NCOx output pin is disabled ; NCOxCON[5] NxOUT: NCOx Output bit ; 1 = NCOx output is high / 0 = NCOx output is low ; NCOxCON[4] NxPOL: NCOx Polarity bit ; 1 = NCOx output signal is active-high / 0 = NCOx output signal is active-low ; NCOxCON[3-1] Unimplemented: Read as e0f. ; NCOxCON[0] NxPFM: NCOx Pulse Frequency Mode bit ; 1 = NCOx operates in Pulse Frequency mode / 0 = NCOx operates in Fixed Duty Cycle mode ; **************************************************************** SELBANK 9 MOVLW B'11000000' MOVWF NCO1CON ; **************************************************************** ; 2.NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER ; NCOxCLK[7-5] NxPWS<2:0>: NCOx Output Pulse Width Select bits(1, 2) ; 111 = 128 NCOx clock periods ; 110 = 64 NCOx clock periods ; 101 = 32 NCOx clock periods ; 100 = 16 NCOx clock periods ; 011 = 8 NCOx clock periods ; 010 = 4 NCOx clock periods ; 001 = 2 NCOx clock periods ; 000 = 1 NCOx clock periods ; NCOxCLK[4-2] Unimplemented: Read as e0f ; NCOxCLK[1-0] NxCKS<1:0>: NCOx Clock Source Select bits ; 11 = NCO1CLK ; 10 = LC1OUT ; 01 = FOSC ; 00 = HFINTOSC (16 MHz) ; **************************************************************** SELBANK 9 MOVLW B'00000001' MOVWF NCO1CLK ; **************************************************************** ; 3.NCOxACCU: NCOx ACCUMULATOR REGISTER ; NCOxACCL: NCOx ACCUMULATOR REGISTER ? LOW BYTE ; NCOxACCL[7:0] NCOxACCL<7:0> NCOx Accumulator, low byte ; NCOxACCH: NCOx ACCUMULATOR REGISTER ? HIGH BYTE ; NCOxACCH[7:0] NCOxACC<15:8> NCOx Accumulator, high byte ; NCOxACCU: NCOx ACCUMULATOR REGISTER ? UPPER BYTE ; NCOxACCU[7-4] Unimplemented: Read as e0f ; NCOxACCU[3-0] NCOxACC<19:16> NCOx Accumulator, upper byte ; **************************************************************** SELBANK 9 MOVLW H'00' MOVWF NCO1ACCU MOVLW H'00' MOVWF NCO1ACCH MOVLW H'00' MOVWF NCO1ACCL ; **************************************************************** ; 4.NCOxINC: NCOx INCREMENT REGISTER ; NCOxINCL: NCOx INCREMENT REGISTER ? LOW BYTE ; NCOxINCL[7-0] NCOxINC<7:0>: NCOx Increment, low byte ; NCOxINCH: NCOx INCREMENT REGISTER ? HIGH BYTE ; NCOxINCL[7-0] NCOxINC<15:8>: NCOx Increment, high byte ; **************************************************************** ; F(Hz)=16MHz*(NCO1INCL)/(2^21) ==> F(Hz)=(NCO1INCL)*7.629394531 ==> NCO1INCL=F(Hz)/7.629394531 ; F(Hz):50Hz 50Hz /7.629394531=>0d6.5536 =>0x6 ; F(Hz):100Hz 100Hz /7.629394531=>0d13.1072=>0xD ; F(Hz):1KHz 1KHz /7.629394531=>0d131.072=>0x83 ; F(Hz):10KHz 10KHz /7.629394531=>0d1310.72=>0x51F ; F(Hz):100KHz 100KHz/7.629394531=>0d13107.2=>0x3333 ; F(Hz):500KHz 500KHz/7.629394531=>0d65536 =>0x10000 SELBANK 9 MOVLW H'33' MOVWF NCO1INCH MOVLW H'33' MOVWF NCO1INCL RETURN ;******************************************************************************************* ; Function Name : SETNCO ; Function : ; Input : ; Output : ; Description : ;******************************************************************************************* SETNCO SELBANK 9 MOVFW ADDAT_H XORLW H'00' BTFSC STATUS,Z GOTO SETNCO1 MOVFW ADDAT_H MOVWF NCO1INCH MOVFW ADDAT_L MOVWF NCO1INCL RETURN SETNCO1 MOVFW ADDAT_L XORLW H'00' BTFSC STATUS,Z GOTO SETNCO2 MOVFW ADDAT_H MOVWF NCO1INCH MOVFW ADDAT_L MOVWF NCO1INCL RETURN SETNCO2 MOVLW H'00' MOVWF NCO1INCH MOVLW H'01' MOVWF NCO1INCL RETURN ;****************************************************************************************** ; Function Name : Wait_1mS ; Title : This function will wait 1 mS ; Input : ; Output : ;****************************************************************************************** WAIT_1MS ; ******************************************************* ; 1.Define T1CON(TIMER1 CONTROL REGISTER) Register ; T1CON(7-6) TMR1CS<1:0>: Timer1 Clock Source Select bits ; 11 =Timer1 clock source is LFINTOSC ; 10 =Timer1 clock source is T1CKI pin (on rising edge) ; 01 =Timer1 clock source is system clock (FOSC) ; 00 =Timer1 clock source is instruction clock (FOSC/4) ; T1CON(5-4) T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits ; 11 = 1:8 Prescale value ; 10 = 1:4 Prescale value ; 01 = 1:2 Prescale value ; 00 = 1:1 Prescale value ; T1CON(3) Unimplemented: Read as e0f ; T1CON(2) T1SYNC: Timer1 Synchronization Control bit ; 1 = Do not synchronize asynchronous clock input ; 0 = Synchronize asynchronous clock input with system clock (FOSC) ; T1CON(1) Unimplemented: Read as e0f ; T1CON(0) TMR1ON: Timer1 On bit ; 1 = Enables Timer1 ; 0 = Stops Timer1 and clears Timer1 gate flip-flop ; ******************************************************* SELBANK 0 ; SET BANK0 MOVLW B'00000001' MOVWF T1CON ; ******************************************************* ; 2.Define T1GCON (TIMER1 GATE CONTROL REGISTER) Register ; T1GCON(7) TMR1GE: Timer1 Gate Enable bit ; If TMR1ON = 0: This bit is ignored ; If TMR1ON = 1: ; 1 = Timer1 counting is controlled by the Timer1 gate function ; 0 = Timer1 counts regardless of Timer1 gate function ; T1GCON(6) T1GPOL: Timer1 Gate Polarity bit ; 1 = Timer1 gate is active-high (Timer1 counts when gate is high) ; 0 = Timer1 gate is active-low (Timer1 counts when gate is low) ; T1GCON(5) T1GTM: Timer1 Gate Toggle Mode bit ; 1 = Timer1 Gate Toggle mode is enabled ; 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared ; T1GCON(4) T1GSPM: Timer1 Gate Single-Pulse Mode bit ; 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate ; 0 = Timer1 Gate Single-Pulse mode is disabled ; T1GCON(3) T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit ; 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge ; 0 = Timer1 gate single-pulse acquisition has completed or has not been started ; T1GCON(2) T1GVAL: Timer1 Gate Current State bit ; Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. ; Unaffected by Timer1 Gate Enable (TMR1GE). ; T1GCON(1-0) T1GSS<1:0>: Timer1 Gate Source Select bits ; 11 = Reserved ; 10 = Comparator 1 optionally synchronized output (sync_C1OUT) ; 01 = Timer0 overflow output ; 00 = Timer1 gate pin ; ******************************************************* MOVLW B'00000000' MOVWF T1GCON ; ******************************************************* ; 3.Define TMR1 Register ; ******************************************************* ; TMR1 data ( OSC:16MHz, FOSC/4, 1:1 Prescale value, 0.01[S];1000Hz ) ; 10mS(100Hz): 16MHz / 4(FOSC/4) / 1(Prescale) / 1000(1000Hz)==> 0d4,000(Count) ==> 0x0FA0(Count) ; TMR1 = 0xFFFF - 0x0FA0 ==> 0xF05F ; TMR1 data ( OSC:16MHz, FOSC/4, 1:8 Prescale value, 0.01[S];100Hz ) ; 10mS(100Hz): 16MHz / 4(FOSC/4) / 8(Prescale) / 100(100Hz)==> 0d5,000(Count) ==> 0x1388(Count) ; TMR1 = 0xFFFF - 0x1388 ==> 0xEC77 ; TMR1 data ( OSC:16MHz, FOSC/4, 1:8 Prescale value, 0.1[S];10Hz ) ; 100mS(10Hz): 16MHz / 4(FOSC/4) / 8(Prescale) / 10(10Hz) ==> 0d50,000(Count) ==> 0xC350(Count) ; TMR1 = 0xFFFF - 0xC350 ==> 0x3CAF MOVLW H'F0' MOVWF TMR1H MOVLW H'5F' MOVWF TMR1L ; ******************************************************* ; 4.Timer ; ******************************************************* BCF PIR1,TMR1IF BTFSS PIR1,TMR1IF GOTO $-1 RETURN ;****************************************************************************************** ; Program : INTADC ; Title : ; Input : ; Output : ;****************************************************************************************** INTADC ; ******************************************************* ; 1.Define ADCON0(A/D CONTROL REGISTER 0) Register ; ADCON0(7) Unimplemented: Read as e0f ; ADCON0(6-2) CHS<4:0>: Analog Channel Select bits ; 00000 = AN0 ; 00001 = AN1 ; 00010 = AN2 ; 00011 = AN3 ; 00100 = Reserved ; E ; E ; E ; 11100 = Reserved. No channel connected. ; 11101 = Temperature Indicator ; 11110 = DAC (Digital-to-Analog Converter) ; 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output ; ADCON0(1) GO/DONE: A/D Conversion Status bit ; 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. ; This bit is automatically cleared by hardware when the A/D conversion has completed. ; 0 = A/D conversion completed/not in progress ; ADCON0(0) ADON: ADC Enable bit ; 1 = ADC is enabled ; 0 = ADC is disabled and consumes no operating current ; ******************************************************* SELBANK 1 ; SET BANK1 MOVLW B'00000001' MOVWF ADCON0 ; ******************************************************* ; 2.Define ADCON1(A/D CONTROL REGISTER 1) Register ; ADCON1(7) ADFM: A/D Result Format Select bit ; 1 = Right justified. Six Most Significant bits of ADRESH are set to e0f when the conversion result is loaded. ; 0 = Left justified. Six Least Significant bits of ADRESL are set to e0f when the conversion result is loaded. ; ADCON1(6-4) ADCS<2:0>: A/D Conversion Clock Select bits ; 000 = FOSC/2 ; 001 = FOSC/8 ; 010 = FOSC/32 ; 011 = FRC (clock supplied from a dedicated RC oscillator) ; 100 = FOSC/4 ; 101 = FOSC/16 ; 110 = FOSC/64 ; 111 = FRC (clock supplied from a dedicated RC oscillator) ; ADCON1(3-2) Unimplemented: Read as e0f ; ADCON1(1-0) ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits ; 00 = VREF+ is connected to VDD ; 01 = Reserved ; 10 = VREF+ is connected to external VREF+ pin(1) ; 11 = Reserved ; ******************************************************* SELBANK 1 ; SET BANK1 MOVLW B'11100000' MOVWF ADCON1 ; ******************************************************* ; 3.Define ADCON2(A/D CONTROL REGISTER 2) Register ; ADCON2(7-4) TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits ; 0000 = No auto-conversion trigger selected ; 0001 = Reserved ; 0010 = Reserved ; 0011 = TMR0 Overflow ; 0100 = TMR1 Overflow ; 0101 = TMR2 Match to PR2 ; 0110 = C1OUT ; 0111 = Reserved ; 1000 = CLC1 ; 1001 = CLC2 ; 1010 = Reserved ; 1011 = Reserved ; 1100 = Reserved ; 1101 = Reserved ; 1110 = Reserved ; 1111 = Reserved ; ADCON2(3-0) Unimplemented: Read as e0f ; ******************************************************* SELBANK 1 ; SET BANK1 MOVLW B'00000000' MOVWF ADCON2 SELBANK 0 ; SET BANK0 RETURN ;****************************************************************************************** ; Function Name : GETADC ; Title : ; Input : ; Output : ADDAT_H,ADDAT_L ;****************************************************************************************** GETADC: ; ***************** ; 1.Start A/D Converter ; ***************** ; (1)GO/DONE: A/D Conversion Status bit SELBANK 1 ; SET BANK1 BSF ADCON0,GO_NOT_DONE ; ***************** ; 2.Get data ; ***************** ; (1)Wait for start flag until the completion status SELBANK 1 ; SET BANK1 BTFSC ADCON0,GO_NOT_DONE GOTO $-1 ; (2)Assigned to a variable data SELBANK 1 ; SET BANK1 MOVF ADRESH,W MOVWF ADDAT_H MOVF ADRESL,W MOVWF ADDAT_L SELBANK 0 ; SET BANK0 RETURN END