;****************************************************************************************** ; PIC12F1501 Sample Program : ; Project : ; Program Name : ; Programer : ; Create date : Version 1.0 H26.04.19 ; History : ; Laungage : MPLAB MPASM ; ;****************************************************************************************** ; Description ; OSC : Internal OSC 16MHz ; Assign I/O pins ; RA1 : NCO1, Numerically Controlled Oscillator output. ; RA5 : NCO1CLK, Numerically Controlled Oscillator clock input. ;****************************************************************************************** LIST P=PIC12F1501,ST=OFF,R=DEC INCLUDE "P12F1501.inc" __CONFIG _CONFIG1 , _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _BOREN_OFF & _CLKOUTEN_OFF __CONFIG _CONFIG2 , _WRT_OFF & _STVREN_OFF & _BORV_HI & _LPBOR_OFF & _LVP_OFF ; ; Define GENERAL PURPOSE RAM AREA (80 bytes maximum) 20h-6fh ; TMP_G EQU 20H ; ; Define Common RAM AREA (16 bytes) 70h-7fh ; TMP_C EQU 70H ; ; Define Macro ; SELBANK MACRO #BANK_NO MOVLW #BANK_NO MOVWF BSR ; The active bank is selected by writing the bank number into the Bank Select Register (BSR) ENDM ; ; Program Start ; ORG 0h GOTO START ORG 4h GOTO START START ; ***************************** ; 1.Initialized ; ***************************** ; (1)Define OSC (16MHz, IntOSC) SELBANK 1 ; SET BANK1 MOVLW B'01111010' MOVWF OSCCON ; (2)Define ANSELA Register ; The ANSELA register is used to configure the Input mode of an I/O pin to analog. SELBANK 3 CLRF ANSELA ; All Degital Port ; (3)Define I/O port SELBANK 1 ; SET BANK1 MOVLW B'11111101' MOVWF TRISA ; (4)Initialized NCO Module CALL INITNCO SELBANK 0 ; ***************************** ; 2.Program main ; ***************************** ; (1)Main loop ; Do not do anything MAIN GOTO MAIN ;******************************************************************************************* ; Function Name : INITNCO@@@@ ; Function : Initialize NCO Module ; Input : ; Output : ; Description : ;******************************************************************************************* INITNCO ; **************************************************************** ; 0.APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER ; APFCON[7] CWG1BSEL: Pin Selection bit ; 1 = CWG1B function is on RA4 / 0 = CWG1B function is on RA0 ; APFCON[6] CWG1ASEL: Pin Selection bit ; 1 = CWG1A function is on RA5 / 0 = CWG1A function is on RA2 ; APFCON[5-4] Unimplemented: Read as e0f ; APFCON[3] T1GSEL: Pin Selection bit ; 1 = T1G function is on RA3 / 0 = T1G function is on RA4 ; APFCON[2] Unimplemented: Read as e0f ; APFCON[1] CLC1SEL: Pin Selection bit ; 1 = CLC1 function is on RA4 / 0 = CLC1 function is on RA2 ; APFCON[0] NCO1SEL: Pin Selection bit ; 1 = NCO1 function is on RA5 / 0 = NCO1 function is on RA1 ; **************************************************************** SELBANK 2 MOVLW B'00000000' MOVWF APFCON ; **************************************************************** ; 1.NCOxCON:NCOx CONTROL REGISTER ; NCOxCON[7] NxEN: NCOx Enable bit ; 1 = NCOx module is enabled / 0 = NCOx module is disabled ; NCOxCON[6] NxOE: NCOx Output Enable bit ; 1 = NCOx output pin is enabled / 0 = NCOx output pin is disabled ; NCOxCON[5] NxOUT: NCOx Output bit ; 1 = NCOx output is high / 0 = NCOx output is low ; NCOxCON[4] NxPOL: NCOx Polarity bit ; 1 = NCOx output signal is active-high / 0 = NCOx output signal is active-low ; NCOxCON[3-1] Unimplemented: Read as e0f. ; NCOxCON[0] NxPFM: NCOx Pulse Frequency Mode bit ; 1 = NCOx operates in Pulse Frequency mode / 0 = NCOx operates in Fixed Duty Cycle mode ; **************************************************************** SELBANK 9 MOVLW B'11000000' MOVWF NCO1CON ; **************************************************************** ; 2.NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER ; NCOxCLK[7-5] NxPWS<2:0>: NCOx Output Pulse Width Select bits(1, 2) ; 111 = 128 NCOx clock periods ; 110 = 64 NCOx clock periods ; 101 = 32 NCOx clock periods ; 100 = 16 NCOx clock periods ; 011 = 8 NCOx clock periods ; 010 = 4 NCOx clock periods ; 001 = 2 NCOx clock periods ; 000 = 1 NCOx clock periods ; NCOxCLK[4-2] Unimplemented: Read as e0f ; NCOxCLK[1-0] NxCKS<1:0>: NCOx Clock Source Select bits ; 11 = NCO1CLK ; 10 = LC1OUT ; 01 = FOSC ; 00 = HFINTOSC (16 MHz) ; **************************************************************** SELBANK 9 MOVLW B'00000011' MOVWF NCO1CLK ; **************************************************************** ; 3.NCOxACCU: NCOx ACCUMULATOR REGISTER ; NCOxACCL: NCOx ACCUMULATOR REGISTER ? LOW BYTE ; NCOxACCL[7:0] NCOxACCL<7:0> NCOx Accumulator, low byte ; NCOxACCH: NCOx ACCUMULATOR REGISTER ? HIGH BYTE ; NCOxACCH[7:0] NCOxACC<15:8> NCOx Accumulator, high byte ; NCOxACCU: NCOx ACCUMULATOR REGISTER ? UPPER BYTE ; NCOxACCU[7-4] Unimplemented: Read as e0f ; NCOxACCU[3-0] NCOxACC<19:16> NCOx Accumulator, upper byte ; **************************************************************** SELBANK 9 MOVLW H'00' MOVWF NCO1ACCU MOVLW H'00' MOVWF NCO1ACCH MOVLW H'00' MOVWF NCO1ACCL ; **************************************************************** ; 4.NCOxINC: NCOx INCREMENT REGISTER ; NCOxINCL: NCOx INCREMENT REGISTER ? LOW BYTE ; NCOxINCL[7-0] NCOxINC<7:0>: NCOx Increment, low byte ; NCOxINCH: NCOx INCREMENT REGISTER ? HIGH BYTE ; NCOxINCL[7-0] NCOxINC<15:8>: NCOx Increment, high byte ; **************************************************************** ; F(Hz)=16MHz*(NCO1INCL)/(2^21) ==> F(Hz)=(NCO1INCL)*7.629394531 ==> NCO1INCL=F(Hz)/7.629394531 ; F(Hz):50Hz 50Hz /7.629394531=>0d6.5536 =>0x6 ; F(Hz):100Hz 100Hz /7.629394531=>0d13.1072=>0xD ; F(Hz):1KHz 1KHz /7.629394531=>0d131.072=>0x83 ; F(Hz):10KHz 10KHz /7.629394531=>0d1310.72=>0x51F ; F(Hz):100KHz 100KHz/7.629394531=>0d13107.2=>0x3333 ; F(Hz):500KHz 500KHz/7.629394531=>0d65536 =>0x10000 ; F(Hz)=12.8MHz*(NCO1INCL)/(2^21) ==> F(Hz)=(NCO1INCL)*6.103515625 ==> NCO1INCL=F(Hz)/6.103515625 ; F(Hz):100KHz 100KHz/6.103515625=>0d16384 =>0x4000 SELBANK 9 MOVLW H'40' MOVWF NCO1INCH MOVLW H'00' MOVWF NCO1INCL RETURN END