;****************************************************************************************** ; PIC12F1501 Sample Program : ; Project : ; Program Name : ; Programer : ; Create date : Version 1.0 H26.05.03 ; History : ; Laungage : MPLAB MPASM ; ;****************************************************************************************** ; Description ; OSC : Internal OSC 1MHz ; Assign I/O pins ; RA2 : CLC1, CLC1 function output ;****************************************************************************************** LIST P=PIC12F1501,ST=OFF,R=DEC INCLUDE "P12F1501.inc" __CONFIG _CONFIG1 , _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _BOREN_OFF & _CLKOUTEN_OFF __CONFIG _CONFIG2 , _WRT_OFF & _STVREN_OFF & _BORV_HI & _LPBOR_OFF & _LVP_OFF ; ; Define GENERAL PURPOSE RAM AREA (80 bytes maximum) 20h-6fh ; TMP_G EQU 20H ; ; Define Common RAM AREA (16 bytes) 70h-7fh ; TMP_C EQU 70H C_TMP1 EQU 71H PLAY_C EQU 72H PLAY_H EQU 73H PLAY_L EQU 74H ; ; Define Macro ; SELBANK MACRO #BANK_NO MOVLW #BANK_NO MOVWF BSR ; The active bank is selected by writing the bank number into the Bank Select Register (BSR) ENDM WAIT01 MACRO #TIME_NO MOVLW #TIME_NO CALL WAIT_01S ENDM PLAYSTP MACRO CALL STOP_1 ENDM PLAYDO2 MACRO MOVLW 2 MOVWF PLAY_H MOVLW 39 MOVWF PLAY_L CALL PLAY_1 ENDM PLAYRE2 MACRO MOVLW 2 MOVWF PLAY_H MOVLW 106 MOVWF PLAY_L CALL PLAY_1 ENDM PLAYMI2 MACRO MOVLW 2 MOVWF PLAY_H MOVLW 181 MOVWF PLAY_L CALL PLAY_1 ENDM PLAYFA2 MACRO MOVLW 2 MOVWF PLAY_H MOVLW 222 MOVWF PLAY_L CALL PLAY_1 ENDM PLAYSO2 MACRO MOVLW 3 MOVWF PLAY_H MOVLW 57 MOVWF PLAY_L CALL PLAY_1 ENDM PLAYRA2 MACRO MOVLW 3 MOVWF PLAY_H MOVLW 158 MOVWF PLAY_L CALL PLAY_1 ENDM PLAYSI2 MACRO MOVLW 4 MOVWF PLAY_H MOVLW 16 MOVWF PLAY_L CALL PLAY_1 ENDM PLAYDO3 MACRO MOVLW 4 MOVWF PLAY_H MOVLW 77 MOVWF PLAY_L CALL PLAY_1 ENDM ; ; Program Start ; ORG 0h GOTO START ORG 4h GOTO START START ; ***************************** ; 1.Initialized ; ***************************** ; (1)Define OSC (1MHz, IntOSC) SELBANK 1 ; SET BANK1 ; MOVLW B'01111010' ; 16MHz OSC MOVLW B'01011010' ; 1MHz OSC MOVWF OSCCON ; (2)Define ANSELA Register ; The ANSELA register is used to configure the Input mode of an I/O pin to analog. SELBANK 3 CLRF ANSELA ; All Degital Port ; (3)Define I/O port SELBANK 1 ; SET BANK1 MOVLW B'11111011' MOVWF TRISA ; (4)Initialized NCO Module CALL INITNCO ; (5)Initialized CLC Module CALL INITCLC SELBANK 0 ; ***************************** ; 2.Program main ; ***************************** ; (1)Main loop MAIN ; CALL DEMO01 CALL DEMO02 GOTO MAIN ;******************************************************************************************* ; Function Name : DEMO01@@@@ ; Function : This demo program to play the do-re-mi ; Input : ; Output : ; Description : ;******************************************************************************************* DEMO01 PLAYDO2 PLAYRE2 PLAYMI2 PLAYFA2 PLAYSO2 PLAYRA2 PLAYSI2 PLAYDO3 ; PLAYSTP PLAYSTP RETURN ;******************************************************************************************* ; Function Name : DEMO02@@@@ ; Function : ; Input : ; Output : ; Description : ;******************************************************************************************* DEMO02 PLAYDO2 PLAYDO2 PLAYRE2 PLAYRE2 PLAYMI2 PLAYMI2 PLAYRE2 PLAYSTP PLAYMI2 PLAYMI2 PLAYSO2 PLAYSO2 PLAYRA2 PLAYRA2 PLAYSO2 PLAYSTP PLAYRA2 PLAYRA2 PLAYSO2 PLAYSO2 PLAYMI2 PLAYDO2 PLAYRE2 PLAYSTP PLAYSO2 PLAYSO2 PLAYMI2 PLAYDO2 PLAYRE2 PLAYMI2 PLAYDO2 PLAYSTP RETURN ;******************************************************************************************* ; Function Name : STOP_1@@@@ ; Function : ; Input : ; Output : ; Description : ;******************************************************************************************* STOP_1 ; 1.Wait WAIT01 4 RETURN ;******************************************************************************************* ; Function Name : PLAY_1@@@@ ; Function : ; Input : ; Output : ; Description : ;******************************************************************************************* PLAY_1 ; 1.Set NCO1INCH register SELBANK 9 MOVF PLAY_H,W MOVWF NCO1INCH ; 2.Set NCO1INCL register SELBANK 9 MOVF PLAY_L,W MOVWF NCO1INCL ; 3.CLC ON CALL CLCON ; 4.Wait WAIT01 1 ; 5.CLC OFF CALL CLCOFF ; 6.Wait WAIT01 3 RETURN ;******************************************************************************************* ; Function Name : INITNCO@@@@ ; Function : Initialize NCO Module ; Input : ; Output : ; Description : ;******************************************************************************************* INITNCO ; **************************************************************** ; 0.APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER ; APFCON[7] CWG1BSEL: Pin Selection bit ; 1 = CWG1B function is on RA4 / 0 = CWG1B function is on RA0 ; APFCON[6] CWG1ASEL: Pin Selection bit ; 1 = CWG1A function is on RA5 / 0 = CWG1A function is on RA2 ; APFCON[5-4] Unimplemented: Read as e0f ; APFCON[3] T1GSEL: Pin Selection bit ; 1 = T1G function is on RA3 / 0 = T1G function is on RA4 ; APFCON[2] Unimplemented: Read as e0f ; APFCON[1] CLC1SEL: Pin Selection bit ; 1 = CLC1 function is on RA4 / 0 = CLC1 function is on RA2 ; APFCON[0] NCO1SEL: Pin Selection bit ; 1 = NCO1 function is on RA5 / 0 = NCO1 function is on RA1 ; **************************************************************** ; SELBANK 2 ; MOVLW B'00000000' ; MOVWF APFCON ; **************************************************************** ; 1.NCOxCON:NCOx CONTROL REGISTER ; NCOxCON[7] NxEN: NCOx Enable bit ; 1 = NCOx module is enabled / 0 = NCOx module is disabled ; NCOxCON[6] NxOE: NCOx Output Enable bit ; 1 = NCOx output pin is enabled / 0 = NCOx output pin is disabled ; NCOxCON[5] NxOUT: NCOx Output bit ; 1 = NCOx output is high / 0 = NCOx output is low ; NCOxCON[4] NxPOL: NCOx Polarity bit ; 1 = NCOx output signal is active-high / 0 = NCOx output signal is active-low ; NCOxCON[3-1] Unimplemented: Read as e0f. ; NCOxCON[0] NxPFM: NCOx Pulse Frequency Mode bit ; 1 = NCOx operates in Pulse Frequency mode / 0 = NCOx operates in Fixed Duty Cycle mode ; **************************************************************** SELBANK 9 ; MOVLW B'11000000' MOVLW B'10000000' MOVWF NCO1CON ; **************************************************************** ; 2.NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER ; NCOxCLK[7-5] NxPWS<2:0>: NCOx Output Pulse Width Select bits(1, 2) ; 111 = 128 NCOx clock periods ; 110 = 64 NCOx clock periods ; 101 = 32 NCOx clock periods ; 100 = 16 NCOx clock periods ; 011 = 8 NCOx clock periods ; 010 = 4 NCOx clock periods ; 001 = 2 NCOx clock periods ; 000 = 1 NCOx clock periods ; NCOxCLK[4-2] Unimplemented: Read as e0f ; NCOxCLK[1-0] NxCKS<1:0>: NCOx Clock Source Select bits ; 11 = NCO1CLK ; 10 = LC1OUT ; 01 = FOSC ; 00 = HFINTOSC (16 MHz) ; **************************************************************** SELBANK 9 MOVLW B'00000001' MOVWF NCO1CLK ; **************************************************************** ; 3.NCOxACCU: NCOx ACCUMULATOR REGISTER ; NCOxACCL: NCOx ACCUMULATOR REGISTER ? LOW BYTE ; NCOxACCL[7:0] NCOxACCL<7:0> NCOx Accumulator, low byte ; NCOxACCH: NCOx ACCUMULATOR REGISTER ? HIGH BYTE ; NCOxACCH[7:0] NCOxACC<15:8> NCOx Accumulator, high byte ; NCOxACCU: NCOx ACCUMULATOR REGISTER ? UPPER BYTE ; NCOxACCU[7-4] Unimplemented: Read as e0f ; NCOxACCU[3-0] NCOxACC<19:16> NCOx Accumulator, upper byte ; **************************************************************** SELBANK 9 MOVLW H'00' MOVWF NCO1ACCU MOVLW H'00' MOVWF NCO1ACCH MOVLW H'00' MOVWF NCO1ACCL ; **************************************************************** ; 4.NCOxINC: NCOx INCREMENT REGISTER ; NCOxINCL: NCOx INCREMENT REGISTER ? LOW BYTE ; NCOxINCL[7-0] NCOxINC<7:0>: NCOx Increment, low byte ; NCOxINCH: NCOx INCREMENT REGISTER ? HIGH BYTE ; NCOxINCL[7-0] NCOxINC<15:8>: NCOx Increment, high byte ; **************************************************************** ; F(Hz)=1MHz*(NCO1INCL)/(2^21) ==> F(Hz)=(NCO1INCL)*0.476837 ==> NCO1INCL=F(Hz)/0.476837 ; ; Ra:220.00Hz/0.476837=>461 (H:1 L:206) ; Si:246.94Hz/0.476837=>518 (H:2 L: 8) ; Do:261.63Hz/0.476837=>549 (H:2 L: 39) ; Re:293.66Hz/0.476837=>616 (H:2 L:106) ; Mi:329.63Hz/0.476837=>691 (H:2 L:181) ; Fa:349.23Hz/0.476837=>732 (H:2 L:222) ; So:392.00Hz/0.476837=>822 (H:3 L: 57) ; Ra:440.00Hz/0.476837=>923 (H:3 L:158) ; Si:493.89Hz/0.476837=>1036 (H:4 L: 16) ; Do:523.25Hz/0.476837=>1097 (H:4 L: 77) SELBANK 9 MOVLW H'00' MOVWF NCO1INCH MOVLW H'83' MOVWF NCO1INCL RETURN ;****************************************************************************************** ; Function Name : Wait_01S ; Title : This function will wait n times of 0.1 seconds ; Input : W-reg (n) ; Output : ;****************************************************************************************** WAIT_01S MOVWF C_TMP1 WAIT_01S_1 CALL WAIT_100MS DECFSZ C_TMP1,F GOTO WAIT_01S_1 RETURN ;****************************************************************************************** ; Function Name : Wait_100mS ; Title : This function will wait 100 mS ; Input : ; Output : ;****************************************************************************************** WAIT_100MS ; ******************************************************* ; 1.Define T1CON(TIMER1 CONTROL REGISTER) Register ; T1CON(7-6) TMR1CS<1:0>: Timer1 Clock Source Select bits ; 11 =Timer1 clock source is LFINTOSC ; 10 =Timer1 clock source is T1CKI pin (on rising edge) ; 01 =Timer1 clock source is system clock (FOSC) ; 00 =Timer1 clock source is instruction clock (FOSC/4) ; T1CON(5-4) T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits ; 11 = 1:8 Prescale value ; 10 = 1:4 Prescale value ; 01 = 1:2 Prescale value ; 00 = 1:1 Prescale value ; T1CON(3) Unimplemented: Read as e0f ; T1CON(2) T1SYNC: Timer1 Synchronization Control bit ; 1 = Do not synchronize asynchronous clock input ; 0 = Synchronize asynchronous clock input with system clock (FOSC) ; T1CON(1) Unimplemented: Read as e0f ; T1CON(0) TMR1ON: Timer1 On bit ; 1 = Enables Timer1 ; 0 = Stops Timer1 and clears Timer1 gate flip-flop ; ******************************************************* SELBANK 0 ; SET BANK0 MOVLW B'00000001' MOVWF T1CON ; ******************************************************* ; 2.Define T1GCON (TIMER1 GATE CONTROL REGISTER) Register ; T1GCON(7) TMR1GE: Timer1 Gate Enable bit ; If TMR1ON = 0: This bit is ignored ; If TMR1ON = 1: ; 1 = Timer1 counting is controlled by the Timer1 gate function ; 0 = Timer1 counts regardless of Timer1 gate function ; T1GCON(6) T1GPOL: Timer1 Gate Polarity bit ; 1 = Timer1 gate is active-high (Timer1 counts when gate is high) ; 0 = Timer1 gate is active-low (Timer1 counts when gate is low) ; T1GCON(5) T1GTM: Timer1 Gate Toggle Mode bit ; 1 = Timer1 Gate Toggle mode is enabled ; 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared ; T1GCON(4) T1GSPM: Timer1 Gate Single-Pulse Mode bit ; 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate ; 0 = Timer1 Gate Single-Pulse mode is disabled ; T1GCON(3) T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit ; 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge ; 0 = Timer1 gate single-pulse acquisition has completed or has not been started ; T1GCON(2) T1GVAL: Timer1 Gate Current State bit ; Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. ; Unaffected by Timer1 Gate Enable (TMR1GE). ; T1GCON(1-0) T1GSS<1:0>: Timer1 Gate Source Select bits ; 11 = Reserved ; 10 = Comparator 1 optionally synchronized output (sync_C1OUT) ; 01 = Timer0 overflow output ; 00 = Timer1 gate pin ; ******************************************************* MOVLW B'00000000' MOVWF T1GCON ; ******************************************************* ; 3.Define TMR1 Register ; ******************************************************* ; TMR1 data ( OSC:16MHz, FOSC/4, 1:8 Prescale value, 0.01[S];100Hz ) ; 10mS(100Hz): 16MHz / 4(FOSC/4) / 8(Prescale) / 100(100Hz)==> 0d5,000(Count) ==> 0x1388(Count) ; TMR1 = 0xFFFF - 0x1388 ==> 0xEC77 ; TMR1 data ( OSC:16MHz, FOSC/4, 1:8 Prescale value, 0.1[S];10Hz ) ; 100mS(10Hz): 16MHz / 4(FOSC/4) / 8(Prescale) / 10(10Hz) ==> 0d50,000(Count) ==> 0xC350(Count) ; TMR1 = 0xFFFF - 0xC350 ==> 0x3CAF ; TMR1 data ( OSC:1MHz, FOSC/4, 1:1 Prescale value, 0.1[S];10Hz ) ; 100mS(10Hz): 1MHz / 4(FOSC/4) / 1(Prescale) / 10(10Hz) ==> 0d25,000(Count) ==> 0x61A8(Count) ; TMR1 = 0xFFFF - 0x61A8 ==> 0x9E57 MOVLW H'9E' MOVWF TMR1H MOVLW H'57' MOVWF TMR1L ; ******************************************************* ; 4.Timer ; ******************************************************* BCF PIR1,TMR1IF BTFSS PIR1,TMR1IF GOTO $-1 RETURN ;******************************************************************************************* ; Function Name : INITCLC@@@@ ; Function : Initialize CLC Module ; Input : ; Output : ; Description : ;******************************************************************************************* INITCLC ; **************************************************************** ; 0.APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER ; APFCON[7] CWG1BSEL: Pin Selection bit ; 1 = CWG1B function is on RA4 / 0 = CWG1B function is on RA0 ; APFCON[6] CWG1ASEL: Pin Selection bit ; 1 = CWG1A function is on RA5 / 0 = CWG1A function is on RA2 ; APFCON[5-4] Unimplemented: Read as e0f ; APFCON[3] T1GSEL: Pin Selection bit ; 1 = T1G function is on RA3 / 0 = T1G function is on RA4 ; APFCON[2] Unimplemented: Read as e0f ; APFCON[1] CLC1SEL: Pin Selection bit ; 1 = CLC1 function is on RA4 / 0 = CLC1 function is on RA2 ; APFCON[0] NCO1SEL: Pin Selection bit ; 1 = NCO1 function is on RA5 / 0 = NCO1 function is on RA1 ; **************************************************************** SELBANK 2 MOVLW B'00000000' MOVWF APFCON ; **************************************************************** ; 1.CLCxGLS0: GATE 1 LOGIC SELECT REGISTER ; CLCxGLS0[7] LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit ; 1 = lcxd4T is gated into lcxg1 / 0 = lcxd4T is not gated into lcxg1 ; CLCxGLS0[6] LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit ; 1 = lcxd4N is gated into lcxg1 / 0 = lcxd4N is not gated into lcxg1 ; CLCxGLS0[5] LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit ; 1 = lcxd3T is gated into lcxg1 / 0 = lcxd3T is not gated into lcxg1 ; CLCxGLS0[4] LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit ; 1 = lcxd3N is gated into lcxg1 / 0 = lcxd3N is not gated into lcxg1 ; CLCxGLS0[3] LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit ; 1 = lcxd2T is gated into lcxg1 / 0 = lcxd2T is not gated into lcxg1 ; CLCxGLS0[2] LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit ; 1 = lcxd2N is gated into lcxg1 / 0 = lcxd2N is not gated into lcxg1 ; CLCxGLS0[1] LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit ; 1 = lcxd1T is gated into lcxg1 / 0 = lcxd1T is not gated into lcxg1 ; CLCxGLS0[0] LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit ; 1 = lcxd1N is gated into lcxg1 / 0 = lcxd1N is not gated into lcxg1 ; **************************************************************** SELBANK 30 ; MOVLW B'01010000' ; MOVLW B'00010000' MOVLW B'00010001' ; MOVLW B'00000001' MOVWF CLC1GLS0 ; **************************************************************** ; 2.CLCxGLS1:GATE 2 LOGIC SELECT REGISTER ; CLCxGLS1[7] LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit ; 1 = lcxd4T is gated into lcxg2 / 0 = lcxd4T is not gated into lcxg2 ; CLCxGLS1[6] LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit ; 1 = lcxd4N is gated into lcxg2 / 0 = lcxd4N is not gated into lcxg2 ; CLCxGLS1[5] LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit ; 1 = lcxd3T is gated into lcxg2 / 0 = lcxd3T is not gated into lcxg2 ; CLCxGLS1[4] LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit ; 1 = lcxd3N is gated into lcxg2 / 0 = lcxd3N is not gated into lcxg2 ; CLCxGLS1[3] LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit ; 1 = lcxd2T is gated into lcxg2 / 0 = lcxd2T is not gated into lcxg2 ; CLCxGLS1[2] LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit ; 1 = lcxd2N is gated into lcxg2 / 0 = lcxd2N is not gated into lcxg2 ; CLCxGLS1[1] LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit ; 1 = lcxd1T is gated into lcxg2 / 0 = lcxd1T is not gated into lcxg2 ; CLCxGLS1[0] LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit ; 1 = lcxd1N is gated into lcxg2 / 0 = lcxd1N is not gated into lcxg2 ; **************************************************************** SELBANK 30 MOVLW B'00000000' MOVWF CLC1GLS1 ; **************************************************************** ; 3.CLCxGLS2: GATE 3 LOGIC SELECT REGISTER ; CLCxGLS2[7] LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit ; 1 = lcxd4T is gated into lcxg3 / 0 = lcxd4T is not gated into lcxg3 ; CLCxGLS2[6] LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit ; 1 = lcxd4N is gated into lcxg3 / 0 = lcxd4N is not gated into lcxg3 ; CLCxGLS2[5] LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit ; 1 = lcxd3T is gated into lcxg3 / 0 = lcxd3T is not gated into lcxg3 ; CLCxGLS2[4] LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit ; 1 = lcxd3N is gated into lcxg3 / 0 = lcxd3N is not gated into lcxg3 ; CLCxGLS2[3] LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit ; 1 = lcxd2T is gated into lcxg3 / 0 = lcxd2T is not gated into lcxg3 ; CLCxGLS2[2] LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit ; 1 = lcxd2N is gated into lcxg3 / 0 = lcxd2N is not gated into lcxg3 ; CLCxGLS2[1] LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit ; 1 = lcxd1T is gated into lcxg3 / 0 = lcxd1T is not gated into lcxg3 ; CLCxGLS2[0] LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit ; 1 = lcxd1N is gated into lcxg3 / 0 = lcxd1N is not gated into lcxg3 ; **************************************************************** SELBANK 30 MOVLW B'00000000' MOVWF CLC1GLS2 ; **************************************************************** ; 4.CLCxGLS3: GATE 4 LOGIC SELECT REGISTER ; CLCxGLS3[7] LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit ; 1 = lcxd4T is gated into lcxg4 / 0 = lcxd4T is not gated into lcxg4 ; CLCxGLS3[6] LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit ; 1 = lcxd4N is gated into lcxg4 / 0 = lcxd4N is not gated into lcxg4 ; CLCxGLS3[5] LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit ; 1 = lcxd3T is gated into lcxg4 / 0 = lcxd3T is not gated into lcxg4 ; CLCxGLS3[4] LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit ; 1 = lcxd3N is gated into lcxg4 / 0 = lcxd3N is not gated into lcxg4 ; CLCxGLS3[3] LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit ; 1 = lcxd2T is gated into lcxg4 / 0 = lcxd2T is not gated into lcxg4 ; CLCxGLS3[2] LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit ; 1 = lcxd2N is gated into lcxg4 / 0 = lcxd2N is not gated into lcxg4 ; CLCxGLS3[1] LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit ; 1 = lcxd1T is gated into lcxg4 / 0 = lcxd1T is not gated into lcxg4 ; CLCxGLS3[0] LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit ; 1 = lcxd1N is gated into lcxg4 / 0 = lcxd1N is not gated into lcxg4 ; **************************************************************** SELBANK 30 MOVLW B'00000000' MOVWF CLC1GLS3 ; **************************************************************** ; 5.CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER ; CLCxSEL0[7] Unimplemented: Read as e0f ; CLCxSEL0[6-4] LCxD2S<2:0>: Input Data 2 Selection Control bits ; 111 = CLCxIN[11] is selected for lcxd2 ; 110 = CLCxIN[10] is selected for lcxd2 ; 101 = CLCxIN[9] is selected for lcxd2 ; 100 = CLCxIN[8] is selected for lcxd2 ; 011 = CLCxIN[7] is selected for lcxd2 ; 010 = CLCxIN[6] is selected for lcxd2 ; 001 = CLCxIN[5] is selected for lcxd2 ; 000 = CLCxIN[4] is selected for lcxd2 ; CLCxSEL0[3] Unimplemented: Read as e0f ; CLCxSEL0[2-0] LCxD1S<2:0>: Input Data 1 Selection Control bits ; 111 = CLCxIN[7] is selected for lcxd1 ; 110 = CLCxIN[6] is selected for lcxd1 ; 101 = CLCxIN[5] is selected for lcxd1 ; 100 = CLCxIN[4] is selected for lcxd1 ; 011 = CLCxIN[3] is selected for lcxd1 ; 010 = CLCxIN[2] is selected for lcxd1 ; 001 = CLCxIN[1] is selected for lcxd1 ; 000 = CLCxIN[0] is selected for lcxd1 ; **************************************************************** ; Data Input lcxd1-D1S lcxd2-D2S lcxd3-D3S lcxd4-D4S CLC-1 CLC-2 ; CLCxIN[0] 000 - - 100 CLC1IN0 CLC2IN0 ; CLCxIN[1] 001 - - 101 CLC1IN1 CLC2IN1 ; CLCxIN[2] 010 - - 110 sync_C1OUT sync_C1OUT ; CLCxIN[3] 011 - - 111 Reserved Reserved ; CLCxIN[4] 100 000 - - FOSC FOSC ; CLCxIN[5] 101 001 - - TMR0IF TMR0IF ; CLCxIN[6] 110 010 - - TMR1IF TMR1IF ; CLCxIN[7] 111 011 - - TMR2 = PR2 TMR2 = PR2 ; CLCxIN[8] - 100 000 - lc1_out lc1_out ; CLCxIN[9] - 101 001 - lc2_out lc2_out ; CLCxIN[10] - 110 010 - Reserved Reserved ; CLCxIN[11] - 111 011 - Reserved Reserved ; CLCxIN[12] - - 100 000 NCO1OUT LFINTOSC ; CLCxIN[13] - - 101 001 HFINTOSC ADFRC ; CLCxIN[14] - - 110 010 PWM3OUT PWM1OUT ; CLCxIN[15] - - 111 011 PWM4OUT PWM2OUT ; **************************************************************** SELBANK 30 ; MOVLW B'00000001' ; Select CLC1IN1 MOVLW B'00000100' ; Select FOSC MOVWF CLC1SEL0 ; **************************************************************** ; 6.CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER ; CLCxSEL1[7] Unimplemented: Read as e0f ; CLCxSEL1[6-4] LCxD4S<2:0>: Input Data 4 Selection Control bits ; 111 = CLCxIN[11] is selected for lcxd4 ; 110 = CLCxIN[10] is selected for lcxd4 ; 101 = CLCxIN[9] is selected for lcxd4 ; 100 = CLCxIN[8] is selected for lcxd4 ; 011 = CLCxIN[7] is selected for lcxd4 ; 010 = CLCxIN[6] is selected for lcxd4 ; 001 = CLCxIN[5] is selected for lcxd4 ; 000 = CLCxIN[4] is selected for lcxd4 ; CLCxSEL1[3] Unimplemented: Read as e0f ; CLCxSEL1[2-0] LCxD3S<2:0>: Input Data 3 Selection Control bits ; 111 = CLCxIN[7] is selected for lcxd3 ; 110 = CLCxIN[6] is selected for lcxd3 ; 101 = CLCxIN[5] is selected for lcxd3 ; 100 = CLCxIN[4] is selected for lcxd3 ; 011 = CLCxIN[3] is selected for lcxd3 ; 010 = CLCxIN[2] is selected for lcxd3 ; 001 = CLCxIN[1] is selected for lcxd3 ; 000 = CLCxIN[0] is selected for lcxd3 ; **************************************************************** ; Data Input lcxd1-D1S lcxd2-D2S lcxd3-D3S lcxd4-D4S CLC-1 CLC-2 ; CLCxIN[0] 000 - - 100 CLC1IN0 CLC2IN0 ; CLCxIN[1] 001 - - 101 CLC1IN1 CLC2IN1 ; CLCxIN[2] 010 - - 110 sync_C1OUT sync_C1OUT ; CLCxIN[3] 011 - - 111 Reserved Reserved ; CLCxIN[4] 100 000 - - FOSC FOSC ; CLCxIN[5] 101 001 - - TMR0IF TMR0IF ; CLCxIN[6] 110 010 - - TMR1IF TMR1IF ; CLCxIN[7] 111 011 - - TMR2 = PR2 TMR2 = PR2 ; CLCxIN[8] - 100 000 - lc1_out lc1_out ; CLCxIN[9] - 101 001 - lc2_out lc2_out ; CLCxIN[10] - 110 010 - Reserved Reserved ; CLCxIN[11] - 111 011 - Reserved Reserved ; CLCxIN[12] - - 100 000 NCO1OUT LFINTOSC ; CLCxIN[13] - - 101 001 HFINTOSC ADFRC ; CLCxIN[14] - - 110 010 PWM3OUT PWM1OUT ; CLCxIN[15] - - 111 011 PWM4OUT PWM2OUT ; **************************************************************** SELBANK 30 MOVLW B'00000100' ; Select NCO1OUT MOVWF CLC1SEL1 ; **************************************************************** ; 7.CLCxPOL: SIGNAL POLARITY CONTROL REGISTER ; CLCxPOL[7] LCxPOL: LCOUT Polarity Control bit ; 1 = The output of the logic cell is inverted ; 0 = The output of the logic cell is not inverted ; CLCxPOL[6-4] Unimplemented: Read as e0f ; CLCxPOL[3] LCxG4POL: Gate 4 Output Polarity Control bit ; 1 = The output of gate 4 is inverted when applied to the logic cell ; 0 = The output of gate 4 is not inverted ; CLCxPOL[2] LCxG3POL: Gate 3 Output Polarity Control bit ; 1 = The output of gate 3 is inverted when applied to the logic cell ; 0 = The output of gate 3 is not inverted ; CLCxPOL[1] LCxG2POL: Gate 2 Output Polarity Control bit ; 1 = The output of gate 2 is inverted when applied to the logic cell ; 0 = The output of gate 2 is not inverted ; CLCxPOL[0] LCxG1POL: Gate 1 Output Polarity Control bit ; 1 = The output of gate 1 is inverted when applied to the logic cell ; 0 = The output of gate 1 is not inverted ; **************************************************************** SELBANK 30 MOVLW B'10000000' MOVWF CLC1POL ; **************************************************************** ; 8.CLCDATA: CLC DATA OUTPUT ; CLCDATA[7-2] Unimplemented: Read as e0f ; CLCDATA[1] MLC2OUT: Mirror copy of LC2OUT bit ; CLCDATA[0] MLC1OUT: Mirror copy of LC1OUT bit ; **************************************************************** SELBANK 30 MOVLW B'00000000' MOVWF CLCDATA ; **************************************************************** ; 9.CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER ; CLCxCON[7] LCxEN: Configurable Logic Cell Enable bit ; 1 = Configurable logic cell is enabled and mixing input signals ; 0 = Configurable logic cell is disabled and has logic zero output ; CLCxCON[6] LCxOE: Configurable Logic Cell Output Enable bit ; 1 = Configurable logic cell port pin output enabled ; 0 = Configurable logic cell port pin output disabled ; CLCxCON[5] LCxOUT: Configurable Logic Cell Data Output bit ; Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire. ; CLCxCON[4] LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit ; 1 = CLCxIF will be set when a rising edge occurs on lcx_out ; 0 = CLCxIF will not be set ; CLCxCON[3] LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit ; 1 = CLCxIF will be set when a falling edge occurs on lcx_out ; 0 = CLCxIF will not be set ; CLCxCON[2-0] LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits ; 111 = Cell is 1-input transparent latch with S and R ; 110 = Cell is J-K flip-flop with R ; 101 = Cell is 2-input D flip-flop with R ; 100 = Cell is 1-input D flip-flop with S and R ; 011 = Cell is S-R latch ; 010 = Cell is 4-input AND ; 001 = Cell is OR-XOR ; 000 = Cell is AND-OR ; **************************************************************** SELBANK 30 MOVLW B'00000001' MOVWF CLC1CON ; ********************************** ; 10.CLC Enable ; ********************************** ; SELBANK 30 ; BSF CLC1CON,LC1OE ; BSF CLC1CON,LC1EN RETURN ;****************************************************************************************** ; Program : CLCON ; Title : ; Input : ; Output : ;****************************************************************************************** CLCON SELBANK 30 BSF CLC1CON,LC1OE BSF CLC1CON,LC1EN RETURN ;****************************************************************************************** ; Program : CLCOFF ; Title : ; Input : ; Output : ;****************************************************************************************** CLCOFF SELBANK 30 BCF CLC1CON,LC1OE BCF CLC1CON,LC1EN RETURN END