;****************************************************************************************** ; PIC12F1501 Sample Program ; Project : ; Program Name : ; Programer : ; Create date : Version 1.0 H26.10.10 ; History : ; Laungage : MPLAB MPASM ; ;****************************************************************************************** ; Description ; OSC : Internal OSC 16MHz ; Assign I/O pins ; Ra0[O] : CWG1B ; Ra2[O] : CWG1A ; Ra5[O] : PWM4 ;****************************************************************************************** LIST P=PIC12F1501,ST=OFF,R=DEC INCLUDE "P12F1501.inc" __CONFIG _CONFIG1 , _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _BOREN_OFF & _CLKOUTEN_OFF __CONFIG _CONFIG2 , _WRT_OFF & _STVREN_OFF & _BORV_HI & _LPBOR_OFF & _LVP_OFF ; ; Define GENERAL PURPOSE RAM AREA (80 bytes maximum) 20h-6fh ; TMP_G EQU 20H ; ; Define Common RAM AREA (16 bytes) 70h-7fh ; TMP_C EQU 70H ; ; Define Macro ; SELBANK MACRO #BANK_NO MOVLW #BANK_NO MOVWF BSR ; The active bank is selected by writing the bank number into the Bank Select Register (BSR) ENDM ; ; Program Start ; ORG 0h GOTO START ORG 4h GOTO START START ; ***************************** ; 1.Initialized ; ***************************** ; (1)Define OSC (16MHz, IntOSC) SELBANK 1 ; SET BANK1 MOVLW B'01111010' MOVWF OSCCON ; (2)Define ANSELA Register SELBANK 3 CLRF ANSELA ; All Degital Port ; (3)Define I/O port SELBANK 1 ; SET BANK1 MOVLW B'11011010' MOVWF TRISA ; (4)Initialized PWM CALL INITPWM ; (5)Set PWM Value SELBANK 12 ; MOVLW H'3F' ; Duty 25 % ( 0xff * 0.25 ==> 0x3F) MOVLW H'7F' ; Duty 50 % ( 0xff * 0.50 ==> 0x7F) ; MOVLW H'BF' ; Duty 75 % ( 0xff * 0.75 ==> 0xBF) MOVWF PWM4DCH ; (6)Initialized CWG CALL INITCWG ; ***************************** ; 2.Program main ; ***************************** ; (1)Main loop MAIN GOTO MAIN ;****************************************************************************************** ; Program : INITPWM ; Title : ; Input : ; Output : ;****************************************************************************************** INITPWM ; ******************************************************* ; 1.Define T2CON: TIMER2 CONTROL REGISTER ; T2CON[7] Unimplemented: Read as e0f ; T2CON[6-3] T2OUTPS<3:0>: Timer2 Output Postscaler Select bits ; 0000 = 1:1 Postscaler ; 0001 = 1:2 Postscaler ; 0010 = 1:3 Postscaler ; 0011 = 1:4 Postscaler ; 0100 = 1:5 Postscaler ; 0101 = 1:6 Postscaler ; 0110 = 1:7 Postscaler ; 0111 = 1:8 Postscaler ; 1000 = 1:9 Postscaler ; 1001 = 1:10 Postscaler ; 1010 = 1:11 Postscaler ; 1011 = 1:12 Postscaler ; 1100 = 1:13 Postscaler ; 1101 = 1:14 Postscaler ; 1110 = 1:15 Postscaler ; 1111 = 1:16 Postscaler ; T2CON[2] TMR2ON: Timer2 On bit ; 1 = Timer2 is on, 0 = Timer2 is off ; T2CON[1-0] T2CKPS<1:0>: Timer2 Clock Prescale Select bits ; 00 = Prescaler is 1 ; 01 = Prescaler is 4 ; 10 = Prescaler is 16 ; 11 = Prescaler is 64 ; ******************************************************* SELBANK 0 MOVLW B'00000100' MOVWF T2CON ; ******************************************************* ; 2.Define PR2: Timer2 Module Period Register ; OSC:16MHz / 0xFF / 4 / 1(Prescaler) ==> 15.625[KHz] ; ******************************************************* SELBANK 0 MOVLW H'FF' MOVWF PR2 ; ******************************************************* ; 3.Define PWMxCON: PWM CONTROL REGISTER ; PWMxCON[7] PWMxEN: PWM Module Enable bit ; 1 = PWM module is enabled, 0 = PWM module is disabled ; PWMxCON[6] PWMxOE: PWM Module Output Enable bit ; 1 = Output to PWMx pin is enabled, 0 = Output to PWMx pin is disabled ; PWMxCON[5] PWMxOUT: PWM Module Output Value bit ; PWMxCON[4] PWMxPOL: PWMx Output Polarity Select bit ; 1 = PWM output is active-low, 0 = PWM output is active-high ; PWMxCON[3-0] Unimplemented: Read as e0f ; ******************************************************* SELBANK 12 MOVLW B'11100000' MOVWF PWM4CON ; ******************************************************* ; 4.Define PWMxDCH: PWM DUTY CYCLE HIGH BITS ; PWMxDCH[7-0]: PWM Duty Cycle Most Significant bits ; These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register. ; ******************************************************* SELBANK 12 MOVLW H'7F' MOVWF PWM4DCH ; ******************************************************* ; 5.Define PWMxDCL: PWM DUTY CYCLE LOW BITS ; PWMxDCL[7:6]: PWM Duty Cycle Least Significant bits ; These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register. ; PWMxDCL[5-0]: Unimplemented: Read as e0f ; ******************************************************* SELBANK 12 MOVLW H'00' MOVWF PWM4DCL SELBANK 0 ; SET BANK0 RETURN ;****************************************************************************************** ; Program : INITCWG ; Title : ; Input : ; Output : ;****************************************************************************************** INITCWG ; ******************************************************* ; 1.Define CWGxCON0: CWG CONTROL REGISTER 0 ; CWG1CON0[7] GxEN: CWGx Enable bit ; 1 = Module is enabled / 0 = Module is disabled ; CWG1CON0[6] GxOEB: CWGxB Output Enable bit ; 1 = CWGxB is available on appropriate I/O pin / 0 = CWGxB is not available on appropriate I/O pin ; CWG1CON0[5] GxOEA: CWGxA Output Enable bit ; 1 = CWGxA is available on appropriate I/O pin / 0 = CWGxA is not available on appropriate I/O pin ; CWG1CON0[4] GxPOLB: CWGxB Output Polarity bit ; 1 = Output is inverted polarity / 0 = Output is normal polarity ; CWG1CON0[3] GxPOLA: CWGxA Output Polarity bit ; 1 = Output is inverted polarity / 0 = Output is normal polarity ; CWG1CON0[2-1] Unimplemented: Read as e0f ; CWG1CON0[0] GxCS0: CWGx Clock Source bit ; 1 = HFINTOSC / 0 = FOSC ; ******************************************************* SELBANK 13 MOVLW B'11100000' MOVWF CWG1CON0 ; ******************************************************* ; 2.Define CWGxCON1: CWG CONTROL REGISTER 1 ; CWGxCON1[7-6] GxASDLB<1:0>: CWGx Shutdown State for CWGxB ; When an auto shutdown event is present (GxASE = 1): ; 11 = CWGxB pin is driven to e1f, regardless of the setting of the GxPOLB bit. ; 10 = CWGxB pin is driven to e0f, regardless of the setting of the GxPOLB bit. ; 01 = CWGxB pin is tri-stated ; 00 = CWGxB pin is driven to itfs inactive state after the selected dead-band interval. GxPOLB still will control the polarity of the output. ; CWGxCON1[5-4] GxASDLA<1:0>: CWGx Shutdown State for CWGxA ; When an auto shutdown event is present (GxASE = 1): ; 11 = CWGxA pin is driven to e1f, regardless of the setting of the GxPOLA bit. ; 10 = CWGxA pin is driven to e0f, regardless of the setting of the GxPOLA bit. ; 01 = CWGxA pin is tri-stated ; 00 = CWGxA pin is driven to itfs inactive state after the selected dead-band interval. GxPOLA still will control the polarity of the output. ; CWGxCON1[3] Unimplemented: Read as e0f ; CWGxCON1[2-0] GxIS<2:0>: CWGx Input Source Select bits ; 111 = LC1OUT ; 110 = N1OUT ; 101 = PWM4OUT ; 100 = PWM3OUT ; 011 = PWM2OUT ; 010 = PWM1OUT ; 001 = async_C1OUT ; 000 = Reserved ; ******************************************************* SELBANK 13 MOVLW B'00000101' MOVWF CWG1CON1 ; ******************************************************* ; 3.Define CWGxCON2: CWG CONTROL REGISTER 2 ; CWG1CON2[7] G1ASE: Auto-Shutdown Event Status bit ; 1 = An auto-shutdown event has occurred / 0 = No auto-shutdown event has occurred ; CWG1CON2[6] G1ARSEN: Auto-Restart Enable bit ; 1 = Auto-restart is enabled / 0 = Auto-restart is disabled ; CWG1CON2[5-3] Unimplemented: Read as e0f ; CWG1CON2[2] G1ASDC1: CWG Auto-shutdown on Comparator 1 Enable bit ; 1 = Shutdown when Comparator 1 output is high / 0 = Comparator 1 output has no effect on shutdown ; CWG1CON2[1] G1ASDFLT: CWG Auto-shutdown on FLT Enable bit ; 1 = Shutdown when CWG1FLT in put is low / 0 = CWG1FLT input has no effect on shutdown ; CWG1CON2[0] G1ASDCLC2: CWG Auto-shutdown on CLC2 Enable bit ; 1 = Shutdown when LC2OUT is high / 0 = LC2OUT has no effect on shutdown ; ******************************************************* SELBANK 13 MOVLW B'00000000' MOVWF CWG1CON2 ; ******************************************************* ; 4.Define CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING DEAD-BAND COUNT REGISTER ; CWG1DBR[7-6] Unimplemented: Read as e0f ; CWG1DBR[5-0] CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising counts ; 11 1111 = 63-64 counts of dead band ; 11 1110 = 62-63 counts of dead band ; * * ; * * ; * ; 00 0010 = 2-3 counts of dead band ; 00 0001 = 1-2 counts of dead band ; 00 0000 = 0 counts of dead band ; ******************************************************* SELBANK 13 MOVLW B'00111111' MOVWF CWG1DBR ; ******************************************************* ; 5.Define CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING DEAD-BAND COUNT REGISTER ; CWGxDBF[7-6] Unimplemented: Read as e0f ; CWGxDBF[5-0] CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling counts ; 11 1111 = 63-64 counts of dead band ; 11 1110 = 62-63 counts of dead band ; * * ; * * ; * ; 00 0010 = 2-3 counts of dead band ; 00 0001 = 1-2 counts of dead band ; 00 0000 = 0 counts of dead band. Dead-band generation is bypassed ; ******************************************************* SELBANK 13 MOVLW B'00111111' MOVWF CWG1DBF SELBANK 0 ; SET BANK0 RETURN END