;****************************************************************************************** ; PIC12F1822 Sample Program ; Project : ; Program Name : ; Programer : ; Create date : Version 1.0 H23.06.09 ; History : ; Laungage : MPLAB MPASM ;****************************************************************************************** ; (1)Description ; OSC : Internal OSC 16MHz ;****************************************************************************************** LIST P=PIC12F1822,ST=OFF,R=DEC INCLUDE "P12F1822.inc" __CONFIG _CONFIG1 , _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF ; __CONFIG _CONFIG1 , _FOSC_INTOSC & _WDTE_OFF & _PWRTE_OFF & _MCLRE_OFF & _CP_OFF & _CPD_OFF & _BOREN_OFF & _CLKOUTEN_ON & _IESO_OFF & _FCMEN_OFF ; __CONFIG _CONFIG2 , _WRT_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_25 & _LVP_OFF __CONFIG _CONFIG2 , _WRT_OFF & _PLLEN_ON & _STVREN_OFF & _BORV_25 & _LVP_OFF ; ; Define GENERAL PURPOSE RAM AREA (80 bytes maximum) ; TMP_G EQU 20H ; ; Define Common RAM AREA (16 bytes) ; TMP_C EQU 70H WAT1M1 EQU 71H ; Define Macro SELBANK MACRO #BANK_NO MOVLW #BANK_NO MOVWF BSR ENDM ORG 0h GOTO START ORG 4h GOTO START START ; ***************************** ; 1.Initialized Segment ; ***************************** ; (1)Define OSC SELBANK 1 ; SET BANK1 ; MOVLW B'11111010' ; 16MHz MOVLW B'11110000' ; 32MHz MOVWF OSCCON ; (2)Define I/O port SELBANK 1 ; SET BANK1 MOVLW B'00111111' MOVWF TRISA SELBANK 0 ; SET BANK0 ; (3)Define I/O port CALL INTRCM ; ***************************** ; 2.Program main ; ***************************** ; (1)Main loop MAIN GOTO MAIN ;****************************************************************************************** ; Program : INTRCM ; Title : ; Input : ; Output : ; Description : ;****************************************************************************************** INTRCM ; ******************************************************* ; 1.Define CLKRCON: REFERENCE CLOCK CONTROL REGISTER ; CLKRCON[7] CLKREN: Reference Clock Module Enable bit ; 1 = Reference clock module is enabled ; 0 = Reference clock module is disabled ; CLKRCON[6] CLKROE: Reference Clock Output Enable bit(3) ; 1 = Reference clock output is enabled on CLKR pin ; 0 = Reference clock output disabled on CLKR pin ; CLKRCON[5] CLKRSLR: Reference Clock Slew Rate Control limiting enable bit ; 1 = Slew rate limiting is enabled ; 0 = Slew rate limiting is disabled ; CLKRCON[4-3] CLKRDC<1:0>: Reference Clock Duty Cycle bits ; 11 = Clock outputs duty cycle of 75% ; 10 = Clock outputs duty cycle of 50% ; 01 = Clock outputs duty cycle of 25% ; 00 = Clock outputs duty cycle of 0% ; CLKRCON[2-0] CLKRDIV<2:0> Reference Clock Divider bits ; 111 = Base clock value divided by 128 ; 110 = Base clock value divided by 64 ; 101 = Base clock value divided by 32 ; 100 = Base clock value divided by 16 ; 011 = Base clock value divided by 8 ; 010 = Base clock value divided by 4 ; 001 = Base clock value divided by 2(1) ; 000 = Base clock value(2) ; ; Note 1: In this mode, the 25% and 75% duty cycle accuracy will be dependent on the source clock duty cycle. ; 2: In this mode, the duty cycle will always be equal to the source clock duty cycle, unless a duty ; cycle of 0% is selected. ; 3: To route CLKR to pin, CLKOUTEN of Configuration Word 1 = 1 is required. CLKOUTEN of Configuration ; Word 1 = 0 will result in FOSC/4. See Section 6.3 gConflicts with the CLKR pinh for details ; ******************************************************* SELBANK 7 ; SET BANK7 MOVLW B'11010001' MOVWF CLKRCON SELBANK 0 RETURN END