----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:16:41 11/06/2007 
-- Design Name: 
-- Module Name:    PRG01 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PRG_MAIN is
  PORT(IN_CLK : in  STD_LOGIC;
       IN_DATA_CLK : in  STD_LOGIC;
       IN_DATA : in  STD_LOGIC;
       IN_SW : in  STD_LOGIC;
       OUT_PLS : out  STD_LOGIC
  );
end PRG_MAIN;

architecture rtl of PRG_MAIN is

  COMPONENT OUT_SW
  PORT(
    CLK : IN std_logic;
    SW  : IN std_logic;
    OUT_CLK : out std_logic
      );
  END COMPONENT;


  COMPONENT CNT_BIN
  PORT(
    CLK : IN std_logic;
    QA  : out std_logic
  );
  END COMPONENT;


  COMPONENT CNT_HEX
  PORT(
    CLK : IN std_logic;
    Q0A  : out std_logic;
    Q0B  : out std_logic;
    Q0C  : out std_logic;
    Q0D  : out std_logic;
    Q1A  : out std_logic;
    Q1B  : out std_logic;
    Q1C  : out std_logic;
    Q1D  : out std_logic;
    Q2A  : out std_logic;
    Q2B  : out std_logic;
    Q2C  : out std_logic;
    Q2D  : out std_logic;
    Q3A  : out std_logic;
    Q3B  : out std_logic;
    Q3C  : out std_logic;
    Q3D  : out std_logic;
    Q4A  : out std_logic;
    Q4B  : out std_logic;
    Q4C  : out std_logic;
    Q4D  : out std_logic;
    Q5A  : out std_logic;
    Q5B  : out std_logic;
    Q5C  : out std_logic;
    Q5D  : out std_logic;
	 RST : IN std_logic
  );
  END COMPONENT;
  
  COMPONENT COMPARE_HEX
  PORT(
    IN_A00  : IN std_logic;
    IN_A01  : IN std_logic;
    IN_A02  : IN std_logic;
    IN_A03  : IN std_logic;
	 IN_A04  : IN std_logic;
    IN_A05  : IN std_logic;
    IN_A06  : IN std_logic;
    IN_A07  : IN std_logic;
    IN_A10  : IN std_logic;
    IN_A11  : IN std_logic;
    IN_A12  : IN std_logic;
    IN_A13  : IN std_logic;
	 IN_A14  : IN std_logic;
    IN_A15  : IN std_logic;
    IN_A16  : IN std_logic;
    IN_A17  : IN std_logic;	 
    IN_A20  : IN std_logic;
    IN_A21  : IN std_logic;
    IN_A22  : IN std_logic;
    IN_A23  : IN std_logic;
	 IN_A24  : IN std_logic;
    IN_A25  : IN std_logic;
    IN_A26  : IN std_logic;
    IN_A27  : IN std_logic;
    IN_B00  : IN std_logic;
    IN_B01  : IN std_logic;
    IN_B02  : IN std_logic;
    IN_B03  : IN std_logic;
	 IN_B04  : IN std_logic;
    IN_B05  : IN std_logic;
    IN_B06  : IN std_logic;
    IN_B07  : IN std_logic;	
    IN_B10  : IN std_logic;
    IN_B11  : IN std_logic;
    IN_B12  : IN std_logic;
    IN_B13  : IN std_logic;
	 IN_B14  : IN std_logic;
    IN_B15  : IN std_logic;
    IN_B16  : IN std_logic;
    IN_B17  : IN std_logic;	
	 IN_B20  : IN std_logic;
    IN_B21  : IN std_logic;
    IN_B22  : IN std_logic;
    IN_B23  : IN std_logic;
	 IN_B24  : IN std_logic;
    IN_B25  : IN std_logic;
    IN_B26  : IN std_logic;
    IN_B27  : IN std_logic;	
    OUT_FLG : out std_logic
  );
  END COMPONENT;

  COMPONENT SET_DATA
  PORT(
    CLK : IN std_logic;
	 IN_DATA : IN std_logic;
    P0_0  : out std_logic;
    P0_1  : out std_logic;
    P0_2  : out std_logic;
    P0_3  : out std_logic;
    P0_4  : out std_logic;
    P0_5  : out std_logic;
    P0_6  : out std_logic;
    P0_7  : out std_logic;
    P1_0  : out std_logic;
    P1_1  : out std_logic;
    P1_2  : out std_logic;
    P1_3  : out std_logic;
    P1_4  : out std_logic;
    P1_5  : out std_logic;
    P1_6  : out std_logic;
    P1_7  : out std_logic;	 
    P2_0  : out std_logic;
    P2_1  : out std_logic;
    P2_2  : out std_logic;
    P2_3  : out std_logic;
    P2_4  : out std_logic;
    P2_5  : out std_logic;
    P2_6  : out std_logic;
    P2_7  : out std_logic
  );
  END COMPONENT;


SIGNAL L0A : std_logic;
SIGNAL L0B : std_logic;
SIGNAL L0C : std_logic;
SIGNAL L0D : std_logic;

SIGNAL L1A : std_logic;
SIGNAL L1B : std_logic;
SIGNAL L1C : std_logic;
SIGNAL L1D : std_logic;

SIGNAL L2A : std_logic;
SIGNAL L2B : std_logic;
SIGNAL L2C : std_logic;
SIGNAL L2D : std_logic;

  
SIGNAL L3A : std_logic;
SIGNAL L3B : std_logic;
SIGNAL L3C : std_logic;
SIGNAL L3D : std_logic;

SIGNAL L4A : std_logic;
SIGNAL L4B : std_logic;
SIGNAL L4C : std_logic;
SIGNAL L4D : std_logic;

SIGNAL L5A : std_logic;
SIGNAL L5B : std_logic;
SIGNAL L5C : std_logic;
SIGNAL L5D : std_logic;


SIGNAL P0_0 : std_logic;
SIGNAL P0_1 : std_logic;
SIGNAL P0_2 : std_logic;
SIGNAL P0_3 : std_logic;

SIGNAL P0_4 : std_logic;
SIGNAL P0_5 : std_logic;
SIGNAL P0_6 : std_logic;
SIGNAL P0_7 : std_logic;

SIGNAL P1_0 : std_logic;
SIGNAL P1_1 : std_logic;
SIGNAL P1_2 : std_logic;
SIGNAL P1_3 : std_logic;

  
SIGNAL P1_4 : std_logic;
SIGNAL P1_5 : std_logic;
SIGNAL P1_6 : std_logic;
SIGNAL P1_7 : std_logic;

SIGNAL P2_0 : std_logic;
SIGNAL P2_1 : std_logic;
SIGNAL P2_2 : std_logic;
SIGNAL P2_3 : std_logic;

SIGNAL P2_4 : std_logic;
SIGNAL P2_5 : std_logic;
SIGNAL P2_6 : std_logic;
SIGNAL P2_7 : std_logic;

SIGNAL CHK_RST : std_logic;
SIGNAL TMP_CLK : std_logic;
--SIGNAL IN_SW : std_logic;

begin
--  P0_0 <= '1';
--  P0_1 <= '0';
--  P0_2 <= '0';
--  P0_3 <= '0';  
--  P0_4 <= '0';
--  P0_5 <= '0';
--  P0_6 <= '0';
--  P0_7 <= '0';

--  P1_0 <= '0';
--  P1_1 <= '0';
--  P1_2 <= '0';
--  P1_3 <= '0';  
--  P1_4 <= '0';
--  P1_5 <= '0';
--  P1_6 <= '0';
--  P1_7 <= '0';
  
--  P2_0 <= '0';
--  P2_1 <= '0';
--  P2_2 <= '0';
--  P2_3 <= '0';  
--  P2_4 <= '0';
--  P2_5 <= '0';
--  P2_6 <= '0';
--  P2_7 <= '0';  

--  IN_SW <= '1';
  
  setdat : SET_DATA port map ( 
    CLK => IN_DATA_CLK,
	 IN_DATA => IN_DATA,
    P0_0 => P0_0,
    P0_1 => P0_1,
	 P0_2 => P0_2,
    P0_3 => P0_3,
    P0_4 => P0_4,
    P0_5 => P0_5,
	 P0_6 => P0_6,
    P0_7 => P0_7,
    P1_0 => P1_0,
    P1_1 => P1_1,
	 P1_2 => P1_2,
    P1_3 => P1_3,
    P1_4 => P1_4,
    P1_5 => P1_5,
	 P1_6 => P1_6,
    P1_7 => P1_7,
    P2_0 => P2_0,
    P2_1 => P2_1,
	 P2_2 => P2_2,
    P2_3 => P2_3,
    P2_4 => P2_4,
    P2_5 => P2_5,
	 P2_6 => P2_6,
    P2_7 => P2_7
  );
 
 
  cntb : CNT_BIN port map (
   CLK => CHK_RST,
   QA => OUT_PLS
  );

  cntsw : OUT_SW port map (
    CLK => IN_CLK,
    SW  => IN_SW,
    OUT_CLK => TMP_CLK
      );

  cnt0 : CNT_HEX port map(
    CLK => TMP_CLK ,
    Q0A  => L0A,
    Q0B  => L0B,
    Q0C  => L0C,
    Q0D  => L0D,
    Q1A  => L1A,
    Q1B  => L1B,
    Q1C  => L1C,
    Q1D  => L1D,
    Q2A  => L2A,
    Q2B  => L2B,
    Q2C  => L2C,
    Q2D  => L2D,
    Q3A  => L3A,
    Q3B  => L3B,
    Q3C  => L3C,
    Q3D  => L3D,
	 Q4A  => L4A,
    Q4B  => L4B,
    Q4C  => L4C,
    Q4D  => L4D,
    Q5A  => L5A,
    Q5B  => L5B,
    Q5C  => L5C,
    Q5D  => L5D,
	 RST => CHK_RST
  );

  chk0 : COMPARE_HEX port map(
    IN_A00 => L0A,
    IN_A01 => L0B,
	 IN_A02 => L0C,
	 IN_A03 => L0D,
	 IN_A04 => L1A,
    IN_A05 => L1B,
	 IN_A06 => L1C,
	 IN_A07 => L1D,
	 IN_A10 => L2A,
    IN_A11 => L2B,
	 IN_A12 => L2C,
	 IN_A13 => L2D,
	 IN_A14 => L3A,
    IN_A15 => L3B,
	 IN_A16 => L3C,
	 IN_A17 => L3D,
    IN_A20 => L4A,
    IN_A21 => L4B,
	 IN_A22 => L4C,
	 IN_A23 => L4D,
	 IN_A24 => L5A,
    IN_A25 => L5B,
	 IN_A26 => L5C,
	 IN_A27 => L5D,	 	 
    IN_B00 => P0_0,
    IN_B01 => P0_1,
	 IN_B02 => P0_2,
	 IN_B03 => P0_3,
    IN_B04 => P0_4,
    IN_B05 => P0_5,
	 IN_B06 => P0_6,
	 IN_B07 => P0_7,
    IN_B10 => P1_0,
    IN_B11 => P1_1,
	 IN_B12 => P1_2,
	 IN_B13 => P1_3,
    IN_B14 => P1_4,
    IN_B15 => P1_5,
	 IN_B16 => P1_6,
	 IN_B17 => P1_7,
    IN_B20 => P2_0,
    IN_B21 => P2_1,
	 IN_B22 => P2_2,
	 IN_B23 => P2_3,
    IN_B24 => P2_4,
    IN_B25 => P2_5,
	 IN_B26 => P2_6,
	 IN_B27 => P2_7,
	 OUT_FLG => CHK_RST
  );
  
  
end rtl;