---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:37:02 11/06/2007 -- Design Name: -- Module Name: PRG03 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ENTITY CNT_HEX IS PORT( CLK : IN std_logic; Q0A : out std_logic; Q0B : out std_logic; Q0C : out std_logic; Q0D : out std_logic; Q1A : out std_logic; Q1B : out std_logic; Q1C : out std_logic; Q1D : out std_logic; Q2A : out std_logic; Q2B : out std_logic; Q2C : out std_logic; Q2D : out std_logic; Q3A : out std_logic; Q3B : out std_logic; Q3C : out std_logic; Q3D : out std_logic; Q4A : out std_logic; Q4B : out std_logic; Q4C : out std_logic; Q4D : out std_logic; Q5A : out std_logic; Q5B : out std_logic; Q5C : out std_logic; Q5D : out std_logic; RST : IN std_logic ); END CNT_HEX; ARCHITECTURE rtl of CNT_HEX IS SIGNAL counter_1 : std_logic_vector(23 downto 0); BEGIN PROCESS(CLK) BEGIN -- if(CLK'event and CLK='1') then if(CLK'event and CLK='0') then if( counter_1 = 16777215 ) then counter_1 <= CONV_STD_LOGIC_VECTOR(0,24); else counter_1 <= counter_1 + 1; end if; end if; if(RST='1') then counter_1 <= CONV_STD_LOGIC_VECTOR(0,24); end if; END PROCESS; Q0A <= counter_1(0); Q0B <= counter_1(1); Q0C <= counter_1(2); Q0D <= counter_1(3); Q1A <= counter_1(4); Q1B <= counter_1(5); Q1C <= counter_1(6); Q1D <= counter_1(7); Q2A <= counter_1(8); Q2B <= counter_1(9); Q2C <= counter_1(10); Q2D <= counter_1(11); Q3A <= counter_1(12); Q3B <= counter_1(13); Q3C <= counter_1(14); Q3D <= counter_1(15); Q4A <= counter_1(16); Q4B <= counter_1(17); Q4C <= counter_1(18); Q4D <= counter_1(19); Q5A <= counter_1(20); Q5B <= counter_1(21); Q5C <= counter_1(22); Q5D <= counter_1(23); end rtl;