---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:46:53 11/06/2007 -- Design Name: -- Module Name: PRG04 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ENTITY COMPARE_HEX IS PORT( IN_A00 : IN std_logic; IN_A01 : IN std_logic; IN_A02 : IN std_logic; IN_A03 : IN std_logic; IN_A04 : IN std_logic; IN_A05 : IN std_logic; IN_A06 : IN std_logic; IN_A07 : IN std_logic; IN_A10 : IN std_logic; IN_A11 : IN std_logic; IN_A12 : IN std_logic; IN_A13 : IN std_logic; IN_A14 : IN std_logic; IN_A15 : IN std_logic; IN_A16 : IN std_logic; IN_A17 : IN std_logic; IN_A20 : IN std_logic; IN_A21 : IN std_logic; IN_A22 : IN std_logic; IN_A23 : IN std_logic; IN_A24 : IN std_logic; IN_A25 : IN std_logic; IN_A26 : IN std_logic; IN_A27 : IN std_logic; IN_B00 : IN std_logic; IN_B01 : IN std_logic; IN_B02 : IN std_logic; IN_B03 : IN std_logic; IN_B04 : IN std_logic; IN_B05 : IN std_logic; IN_B06 : IN std_logic; IN_B07 : IN std_logic; IN_B10 : IN std_logic; IN_B11 : IN std_logic; IN_B12 : IN std_logic; IN_B13 : IN std_logic; IN_B14 : IN std_logic; IN_B15 : IN std_logic; IN_B16 : IN std_logic; IN_B17 : IN std_logic; IN_B20 : IN std_logic; IN_B21 : IN std_logic; IN_B22 : IN std_logic; IN_B23 : IN std_logic; IN_B24 : IN std_logic; IN_B25 : IN std_logic; IN_B26 : IN std_logic; IN_B27 : IN std_logic; OUT_FLG : out std_logic ); END COMPARE_HEX; ARCHITECTURE rtl of COMPARE_HEX IS SIGNAL number_0 : std_logic_vector(23 downto 0); SIGNAL number_1 : std_logic_vector(23 downto 0); BEGIN number_0(0) <= IN_A00; number_0(1) <= IN_A01; number_0(2) <= IN_A02; number_0(3) <= IN_A03; number_0(4) <= IN_A04; number_0(5) <= IN_A05; number_0(6) <= IN_A06; number_0(7) <= IN_A07; number_0(8) <= IN_A10; number_0(9) <= IN_A11; number_0(10) <= IN_A12; number_0(11) <= IN_A13; number_0(12) <= IN_A14; number_0(13) <= IN_A15; number_0(14) <= IN_A16; number_0(15) <= IN_A17; number_0(16) <= IN_A20; number_0(17) <= IN_A21; number_0(18) <= IN_A22; number_0(19) <= IN_A23; number_0(20) <= IN_A24; number_0(21) <= IN_A25; number_0(22) <= IN_A26; number_0(23) <= IN_A27; number_1(0) <= IN_B00; number_1(1) <= IN_B01; number_1(2) <= IN_B02; number_1(3) <= IN_B03; number_1(4) <= IN_B04; number_1(5) <= IN_B05; number_1(6) <= IN_B06; number_1(7) <= IN_B07; number_1(8) <= IN_B10; number_1(9) <= IN_B11; number_1(10) <= IN_B12; number_1(11) <= IN_B13; number_1(12) <= IN_B14; number_1(13) <= IN_B15; number_1(14) <= IN_B16; number_1(15) <= IN_B17; number_1(16) <= IN_B20; number_1(17) <= IN_B21; number_1(18) <= IN_B22; number_1(19) <= IN_B23; number_1(20) <= IN_B24; number_1(21) <= IN_B25; number_1(22) <= IN_B26; number_1(23) <= IN_B27; OUT_FLG <= '1' when number_0 = number_1 else '0'; end rtl;