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-- Company: 
-- Engineer: 
-- 
-- Create Date:    11:31:24 11/06/2007 
-- Design Name: 
-- Module Name:    PRG05 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY OUT_SW IS
  PORT( 
    CLK : IN std_logic;
    SW  : IN std_logic;
    OUT_CLK : out std_logic
    );
END OUT_SW;

ARCHITECTURE rtl of OUT_SW IS
  SIGNAL chk_flg : std_logic_vector(1 downto 0); 
BEGIN
  chk_flg(0) <= CLK;
  chk_flg(1) <= SW;
  OUT_CLK <= '1' when chk_flg = 2 else '0';			  
end rtl;