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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:04:31 11/06/2007 
-- Design Name: 
-- Module Name:    PRG06 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY SET_DATA IS
  PORT(
    CLK : IN std_logic;
	 IN_DATA : IN std_logic;
    P0_0  : out std_logic;
    P0_1  : out std_logic;
    P0_2  : out std_logic;
    P0_3  : out std_logic;
    P0_4  : out std_logic;
    P0_5  : out std_logic;
    P0_6  : out std_logic;
    P0_7  : out std_logic;
    P1_0  : out std_logic;
    P1_1  : out std_logic;
    P1_2  : out std_logic;
    P1_3  : out std_logic;
    P1_4  : out std_logic;
    P1_5  : out std_logic;
    P1_6  : out std_logic;
    P1_7  : out std_logic;	 
    P2_0  : out std_logic;
    P2_1  : out std_logic;
    P2_2  : out std_logic;
    P2_3  : out std_logic;
    P2_4  : out std_logic;
    P2_5  : out std_logic;
    P2_6  : out std_logic;
    P2_7  : out std_logic  
    );
END SET_DATA;

ARCHITECTURE rtl of SET_DATA IS
  SIGNAL data_buffer_0 : std_logic_vector(23 downto 0);
BEGIN

  PROCESS(CLK)
  BEGIN
    if(CLK'event and CLK='1') then
--    if(CLK'event and CLK='0') then
       data_buffer_0(23) <= data_buffer_0(22);
		 data_buffer_0(22) <= data_buffer_0(21);
       data_buffer_0(21) <= data_buffer_0(20);
		 data_buffer_0(20) <= data_buffer_0(19);
       data_buffer_0(19) <= data_buffer_0(18);
		 data_buffer_0(18) <= data_buffer_0(17);
       data_buffer_0(17) <= data_buffer_0(16);
		 data_buffer_0(16) <= data_buffer_0(15);
       data_buffer_0(15) <= data_buffer_0(14);
		 data_buffer_0(14) <= data_buffer_0(13);
       data_buffer_0(13) <= data_buffer_0(12);
		 data_buffer_0(12) <= data_buffer_0(11);
       data_buffer_0(11) <= data_buffer_0(10);
		 data_buffer_0(10) <= data_buffer_0(9);
       data_buffer_0(9) <= data_buffer_0(8);
		 data_buffer_0(8) <= data_buffer_0(7);
       data_buffer_0(7) <= data_buffer_0(6);
		 data_buffer_0(6) <= data_buffer_0(5);
       data_buffer_0(5) <= data_buffer_0(4);
		 data_buffer_0(4) <= data_buffer_0(3);
       data_buffer_0(3) <= data_buffer_0(2);
		 data_buffer_0(2) <= data_buffer_0(1);
       data_buffer_0(1) <= data_buffer_0(0);
		 data_buffer_0(0) <= IN_DATA;
	 end if;	
  END PROCESS;
  P0_0 <= data_buffer_0(0);
  P0_1 <= data_buffer_0(1);
  P0_2 <= data_buffer_0(2);
  P0_3 <= data_buffer_0(3);
  P0_4 <= data_buffer_0(4);
  P0_5 <= data_buffer_0(5);
  P0_6 <= data_buffer_0(6);
  P0_7 <= data_buffer_0(7);

  P1_0 <= data_buffer_0(8);
  P1_1 <= data_buffer_0(9);
  P1_2 <= data_buffer_0(10);
  P1_3 <= data_buffer_0(11);
  P1_4 <= data_buffer_0(12);
  P1_5 <= data_buffer_0(13);
  P1_6 <= data_buffer_0(14);
  P1_7 <= data_buffer_0(15);

  P2_0 <= data_buffer_0(16);
  P2_1 <= data_buffer_0(17);
  P2_2 <= data_buffer_0(18);
  P2_3 <= data_buffer_0(19);
  P2_4 <= data_buffer_0(20);
  P2_5 <= data_buffer_0(21);
  P2_6 <= data_buffer_0(22);
  P2_7 <= data_buffer_0(23);

end rtl;