---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:58:17 12/06/2007 -- Design Name: -- Module Name: PROG01 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity PRG_MAIN is PORT(IN_CLK : in STD_LOGIC; P0_0 : IN std_logic; P0_1 : IN std_logic; P0_2 : IN std_logic; P0_3 : IN std_logic; P0_4 : IN std_logic; P0_5 : IN std_logic; P0_6 : IN std_logic; P0_7 : IN std_logic; P1_0 : IN std_logic; P1_1 : IN std_logic; P1_2 : IN std_logic; P1_3 : IN std_logic; P1_4 : IN std_logic; P1_5 : IN std_logic; P1_6 : IN std_logic; P1_7 : IN std_logic; P2_0 : IN std_logic; P2_1 : IN std_logic; P2_2 : IN std_logic; P2_3 : IN std_logic; P2_4 : IN std_logic; P2_5 : IN std_logic; P2_6 : IN std_logic; P2_7 : IN std_logic; OUT_PLS : out STD_LOGIC ); end PRG_MAIN; architecture rtl of PRG_MAIN is COMPONENT CNT_BIN PORT( CLK : IN std_logic; QA : out std_logic ); END COMPONENT; COMPONENT CNT_HEX PORT( CLK : IN std_logic; Q0A : out std_logic; Q0B : out std_logic; Q0C : out std_logic; Q0D : out std_logic; Q0E : out std_logic; Q0F : out std_logic; Q0G : out std_logic; Q0H : out std_logic; Q1A : out std_logic; Q1B : out std_logic; Q1C : out std_logic; Q1D : out std_logic; Q1E : out std_logic; Q1F : out std_logic; Q1G : out std_logic; Q1H : out std_logic; Q2A : out std_logic; Q2B : out std_logic; Q2C : out std_logic; Q2D : out std_logic; Q2E : out std_logic; Q2F : out std_logic; Q2G : out std_logic; Q2H : out std_logic; RST : IN std_logic ); END COMPONENT; COMPONENT COMPARE_HEX PORT( IN_A00 : IN std_logic; IN_A01 : IN std_logic; IN_A02 : IN std_logic; IN_A03 : IN std_logic; IN_A04 : IN std_logic; IN_A05 : IN std_logic; IN_A06 : IN std_logic; IN_A07 : IN std_logic; IN_A10 : IN std_logic; IN_A11 : IN std_logic; IN_A12 : IN std_logic; IN_A13 : IN std_logic; IN_A14 : IN std_logic; IN_A15 : IN std_logic; IN_A16 : IN std_logic; IN_A17 : IN std_logic; IN_A20 : IN std_logic; IN_A21 : IN std_logic; IN_A22 : IN std_logic; IN_A23 : IN std_logic; IN_A24 : IN std_logic; IN_A25 : IN std_logic; IN_A26 : IN std_logic; IN_A27 : IN std_logic; IN_B00 : IN std_logic; IN_B01 : IN std_logic; IN_B02 : IN std_logic; IN_B03 : IN std_logic; IN_B04 : IN std_logic; IN_B05 : IN std_logic; IN_B06 : IN std_logic; IN_B07 : IN std_logic; IN_B10 : IN std_logic; IN_B11 : IN std_logic; IN_B12 : IN std_logic; IN_B13 : IN std_logic; IN_B14 : IN std_logic; IN_B15 : IN std_logic; IN_B16 : IN std_logic; IN_B17 : IN std_logic; IN_B20 : IN std_logic; IN_B21 : IN std_logic; IN_B22 : IN std_logic; IN_B23 : IN std_logic; IN_B24 : IN std_logic; IN_B25 : IN std_logic; IN_B26 : IN std_logic; IN_B27 : IN std_logic; OUT_FLG : out std_logic ); END COMPONENT; SIGNAL L0A : std_logic; SIGNAL L0B : std_logic; SIGNAL L0C : std_logic; SIGNAL L0D : std_logic; SIGNAL L0E : std_logic; SIGNAL L0F : std_logic; SIGNAL L0G : std_logic; SIGNAL L0H : std_logic; SIGNAL L1A : std_logic; SIGNAL L1B : std_logic; SIGNAL L1C : std_logic; SIGNAL L1D : std_logic; SIGNAL L1E : std_logic; SIGNAL L1F : std_logic; SIGNAL L1G : std_logic; SIGNAL L1H : std_logic; SIGNAL L2A : std_logic; SIGNAL L2B : std_logic; SIGNAL L2C : std_logic; SIGNAL L2D : std_logic; SIGNAL L2E : std_logic; SIGNAL L2F : std_logic; SIGNAL L2G : std_logic; SIGNAL L2H : std_logic; SIGNAL TP0_0 : std_logic; SIGNAL TP0_1 : std_logic; SIGNAL TP0_2 : std_logic; SIGNAL TP0_3 : std_logic; SIGNAL TP0_4 : std_logic; SIGNAL TP0_5 : std_logic; SIGNAL TP0_6 : std_logic; SIGNAL TP0_7 : std_logic; SIGNAL TP1_0 : std_logic; SIGNAL TP1_1 : std_logic; SIGNAL TP1_2 : std_logic; SIGNAL TP1_3 : std_logic; SIGNAL TP1_4 : std_logic; SIGNAL TP1_5 : std_logic; SIGNAL TP1_6 : std_logic; SIGNAL TP1_7 : std_logic; SIGNAL TP2_0 : std_logic; SIGNAL TP2_1 : std_logic; SIGNAL TP2_2 : std_logic; SIGNAL TP2_3 : std_logic; SIGNAL TP2_4 : std_logic; SIGNAL TP2_5 : std_logic; SIGNAL TP2_6 : std_logic; SIGNAL TP2_7 : std_logic; SIGNAL TMP_CLK : std_logic; SIGNAL CHK_RST : std_logic; begin -- 100KHz Test Sample : 33MHz/2/165(10100101)==>100KHz TP0_0 <= '1'; TP0_1 <= '0'; TP0_2 <= '1'; TP0_3 <= '0'; TP0_4 <= '0'; TP0_5 <= '1'; TP0_6 <= '0'; TP0_7 <= '1'; TP1_0 <= '0'; TP1_1 <= '0'; TP1_2 <= '0'; TP1_3 <= '0'; TP1_4 <= '0'; TP1_5 <= '0'; TP1_6 <= '0'; TP1_7 <= '0'; TP2_0 <= '0'; TP2_1 <= '0'; TP2_2 <= '0'; TP2_3 <= '0'; TP2_4 <= '0'; TP2_5 <= '0'; TP2_6 <= '0'; TP2_7 <= '0'; cntb : CNT_BIN port map ( CLK => CHK_RST, QA => OUT_PLS ); cnt0 : CNT_HEX port map( CLK => IN_CLK , Q0A => L0A, Q0B => L0B, Q0C => L0C, Q0D => L0D, Q0E => L0E, Q0F => L0F, Q0G => L0G, Q0H => L0H, Q1A => L1A, Q1B => L1B, Q1C => L1C, Q1D => L1D, Q1E => L1E, Q1F => L1F, Q1G => L1G, Q1H => L1H, Q2A => L2A, Q2B => L2B, Q2C => L2C, Q2D => L2D, Q2E => L2E, Q2F => L2F, Q2G => L2G, Q2H => L2H, RST => CHK_RST ); chk0 : COMPARE_HEX port map( IN_A00 => L0A, IN_A01 => L0B, IN_A02 => L0C, IN_A03 => L0D, IN_A04 => L0E, IN_A05 => L0F, IN_A06 => L0G, IN_A07 => L0H, IN_A10 => L1A, IN_A11 => L1B, IN_A12 => L1C, IN_A13 => L1D, IN_A14 => L1E, IN_A15 => L1F, IN_A16 => L1G, IN_A17 => L1H, IN_A20 => L2A, IN_A21 => L2B, IN_A22 => L2C, IN_A23 => L2D, IN_A24 => L2E, IN_A25 => L2F, IN_A26 => L2G, IN_A27 => L2H, IN_B00 => P0_0, IN_B01 => P0_1, IN_B02 => P0_2, IN_B03 => P0_3, IN_B04 => P0_4, IN_B05 => P0_5, IN_B06 => P0_6, IN_B07 => P0_7, IN_B10 => P1_0, IN_B11 => P1_1, IN_B12 => P1_2, IN_B13 => P1_3, IN_B14 => P1_4, IN_B15 => P1_5, IN_B16 => P1_6, IN_B17 => P1_7, IN_B20 => P2_0, IN_B21 => P2_1, IN_B22 => P2_2, IN_B23 => P2_3, IN_B24 => P2_4, IN_B25 => P2_5, IN_B26 => P2_6, IN_B27 => P2_7, OUT_FLG => CHK_RST ); end rtl;