---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11:58:35 12/06/2007 -- Design Name: -- Module Name: PRG02 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ENTITY CNT_BIN IS PORT( CLK : IN std_logic; QA : out std_logic ); END CNT_BIN; ARCHITECTURE rtl of CNT_BIN IS SIGNAL counter_0 : std_logic_vector(1 downto 0); BEGIN PROCESS(CLK) BEGIN -- if(CLK'event and CLK='1') then if(CLK'event and CLK='0') then if( counter_0 = 1 ) then counter_0 <= CONV_STD_LOGIC_VECTOR(0,1); else counter_0 <= counter_0 + 1; end if; end if; END PROCESS; QA <= counter_0(0); end rtl;