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-- Company: 
-- Engineer: 
-- 
-- Create Date:    12:01:10 12/06/2007 
-- Design Name: 
-- Module Name:    PRG03 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY CNT_HEX IS
  PORT(
    CLK : IN std_logic;
    Q0A  : out std_logic;
    Q0B  : out std_logic;
    Q0C  : out std_logic;
    Q0D  : out std_logic;
    Q0E  : out std_logic;
    Q0F  : out std_logic;
    Q0G  : out std_logic;
    Q0H  : out std_logic;
    Q1A  : out std_logic;
    Q1B  : out std_logic;
    Q1C  : out std_logic;
    Q1D  : out std_logic;
    Q1E  : out std_logic;
    Q1F  : out std_logic;
    Q1G  : out std_logic;
    Q1H  : out std_logic;
    Q2A  : out std_logic;
    Q2B  : out std_logic;
    Q2C  : out std_logic;
    Q2D  : out std_logic;
    Q2E  : out std_logic;
    Q2F  : out std_logic;
    Q2G  : out std_logic;
    Q2H  : out std_logic;
    RST : IN std_logic
    );
END CNT_HEX;

ARCHITECTURE rtl of CNT_HEX IS
  SIGNAL counter_1 : std_logic_vector(23 downto 0);
BEGIN

  PROCESS(CLK)
  BEGIN
--    if(CLK'event and CLK='1') then
    if(CLK'event and CLK='0') then
      if( counter_1 = 16777215 ) then
        counter_1 <= CONV_STD_LOGIC_VECTOR(0,24);
      else
        counter_1 <= counter_1 + 1;
      end if;
    end if;
    if(RST='1') then
        counter_1 <= CONV_STD_LOGIC_VECTOR(0,24);
    end if;
  END PROCESS;

  Q0A <= counter_1(0);
  Q0B <= counter_1(1);
  Q0C <= counter_1(2);
  Q0D <= counter_1(3);
  Q0E <= counter_1(4);
  Q0F <= counter_1(5);
  Q0G <= counter_1(6);
  Q0H <= counter_1(7);

  Q1A <= counter_1(8);
  Q1B <= counter_1(9);
  Q1C <= counter_1(10);
  Q1D <= counter_1(11);
  Q1E <= counter_1(12);
  Q1F <= counter_1(13);
  Q1G <= counter_1(14);
  Q1H <= counter_1(15);
  
  Q2A <= counter_1(16);
  Q2B <= counter_1(17);
  Q2C <= counter_1(18);
  Q2D <= counter_1(19);
  Q2E <= counter_1(20);
  Q2F <= counter_1(21);
  Q2G <= counter_1(22);
  Q2H <= counter_1(23);
end rtl;