----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:31:18 08/28/2006 
-- Design Name: 
-- Module Name:    PRG01 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
-- 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity PRG01 is
    PORT(
    OUT_DAT : out  STD_LOGIC;
    IN_DAT : in  STD_LOGIC	);
end PRG01;

architecture Behavioral of PRG01 is
    COMPONENT CNT1
        PORT(
            CLK : IN std_logic;
            Q : out std_logic
          );
    END COMPONENT;
begin
    STEP1 : CNT1 port map(
        CLK => IN_DAT,
        Q  => OUT_DAT
    );

end Behavioral;