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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:34:06 08/28/2006 
-- Design Name: 
-- Module Name:    PRG02 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity CNT1 is  PORT(
    CLK : IN std_logic;
    Q  : out std_logic
    );

end CNT1;

architecture Behavioral of CNT1 is
    SIGNAL counter : std_logic_vector(13 downto 0);
begin
    PROCESS(CLK)
    BEGIN
        if(CLK'event and CLK='1') then
            if( counter = 9999 ) then
                counter <= CONV_STD_LOGIC_VECTOR(0,14);
              else
                counter <= counter + 1;
            end if;
        end if;
    END PROCESS;  
    Q <= counter(13);
end Behavioral;