# **************************************************************************
#  SH7125F Sample Program
#   Program Name : 
#   Programer    :
#   Create date  :  
#   History      :
#   Description  : Cygwin(AS)
# **************************************************************************
#    Memo
#     1.Registor
#        General Registor 32(bit) 
#           R0     : General and Index
#           R1-R14 : General
#           R15    : Hardware SP 
#        System Register
#           PC     : Program Counter
#           PR     : Prociger Register (Prociger return address)
#           MACH,MACL
#        Control Register
#           SR,RS,RE,GBR,VBR,MOD 
#     2.Register and memory map
#        R1 :Tempolary Register
#        R2 :Tempolary Register
#        R14:Base Address
#        @(BASE + 0) : PECRL1 Address
#        @(BASE + 4) : PECRL2 Address
#        @(BASE + 8) : PECRL3 Address
#        @(BASE + 12): PECRL4 Address
#        @(BASE + 16): PEIORL Address
#        @(BASE + 20): PEDRL  Address
#        @(BASE + 24): PEPRL  Address
#        @(BASE + 28): LP 
#        @(BASE + 32): LP1 
#        @(BASE + 36): LED status 
# **************************************************************************

        .text
        .align 1
        .global    _main
_main:
#***************************************
#  1.Initiarize Segment 
#***************************************
#  1.Compute base address
	mov.l	r14,@-r15        ! 
	sts.l	pr,@-r15         ! Function end addrress  
	add	#-40,r15         ! End - data area
	mov	r15,r14          ! BASE address => r14 register   

#  2.Define PORT Register
#   (1)Set Register address 
	mov.w	_PECRL1,r1
	mov.l	r1,@r14          ! @(BASE + 0)  <= PECRL1 Address
	mov.w	_PECRL2,r1
	mov.l	r1,@(4,r14)      ! @(BASE + 4)  <= PECRL2 Address
	mov.w	_PECRL3,r1
	mov.l	r1,@(8,r14)      ! @(BASE + 8)  <= PECRL3 Address
	mov.w	_PECRL4,r1
	mov.l	r1,@(12,r14)     ! @(BASE + 12) <= PECRL4 Address
	mov.w	_PEIORL,r1
	mov.l	r1,@(16,r14)     ! @(BASE + 16) <= PEIORL Address
	mov.w	_PEDRL,r1
	mov.l	r1,@(20,r14)     ! @(BASE + 20) <= PEDRL  Address
	mov.w	_PEPRL,r1
	mov.l	r1,@(24,r14)     ! @(BASE + 24) <= PEPRL  Address
	mov.l	@r14,r2          !  =>R2 register

#   (2)Set PFC Register
#     PECRL1 <= 0
	mov	#0,r1
	mov.w	r1,@r2
	mov.l	@(4,r14),r2

#     PECRL2 <= 0
	mov	#0,r1
	mov.w	r1,@r2
	mov.l	@(8,r14),r2

#     PECRL3 <= 0
	mov	#0,r1
	mov.w	r1,@r2
	mov.l	@(12,r14),r2

#     PECRL4 <= 0
	mov	#0,r1
	mov.w	r1,@r2
	mov.l	@(20,r14),r2

#   (3)Set PEIORL Register : PEIORL <= 0x00FF(word) 
	mov.w	_RET_FF_S,r1
	mov.w	r1,@r2
	mov.l	@(16,r14),r2

#   (4)Set PEDRL Register  : PEDRL <= 0
	mov	#0,r1
	mov.w	r1,@r2

#***************************************
#  2.Main Segment 
#***************************************
_main_s:                         ! Loop
#   (1)Set LED status (Defalt value 0x01)
	mov	r14,r2           ! 
	add	#36,r2           ! R2:@(BASE + 36);LED status 
	mov	#1,r1            !
	mov.w	r1,@r2           ! @(BASE + 36)         <= LED status (0x01)
	mov.l	@(16,r14),r2     ! PEDRL ; @(BASE + 16) <= LED status (0x01)

	mov	r14,r1           ! 
	add	#36,r1           ! R1:@(BASE + 36);LED status
	mov.w	@r1,r1           ! 
	mov.w	r1,@r2           ! R2:@(BASE + 36);LED status         

	mov	#0,r1            ! 
	mov.l	r1,@(32,r14)     ! R1:@(BASE + 36) <= 0x00000000 

#   (2)Main Process
_main_s1:
	mov.l	@(32,r14),r2     ! LP1 ; @(BASE + 32)
	mov	#7,r1            ! R1  : LP1-compare-value <= 7 
	cmp/hi	r1,r2            ! IF (LP1:LP1-compare-value)
	bt	_main_s          ! GOTO
	mov	#0,r1            ! R1 <= 0 
	mov.l	r1,@(28,r14)     ! LP ; @(BASE + 28)

_main_s2:   
	mov.l	@(28,r14),r2     ! R2 <= LP;@(BASE + 28)
	mov.l	_RET_LPNUM_L,r1  ! R1 <= LP-compare-value <= PI_LOOP_NUM 
	cmp/hi	r1,r2            ! IF (LP:LP-compare-value) 
	bt	_main_s3         ! GOTO
	mov.l	@(28,r14),r1     ! LP;@(BASE + 28) => R1
	add	#1,r1            ! R1++
	mov.l	r1,@(28,r14)     ! R1 => LP;@(BASE + 28)
	bra	_main_s2         ! GOTO
	nop

	.align 1
_main_s3:  
	mov	r14,r2           ! Base => R2
	add	#36,r2           ! @(BASE + 36);LED status => R2
	mov	r14,r1           ! @(BASE + 36);LED status => R1
	add	#36,r1           ! R1++ 
	mov.w	@r1,r1           ! 
	extu.w	r1,r1            ! 
	add	r1,r1            ! R1+R1
	mov.w	r1,@r2           ! R1 => @(BASE + 36);LED status
#
	mov.l	@(16,r14),r2     ! PEDRL;@(BASE + 16) => R2
	mov	r14,r1           ! BASE => R1
	add	#36,r1           ! @(BASE + 36);LED status = R1
	mov.w	@r1,r1           !
	mov.w	r1,@r2           ! R1 => @(BASE + 36);LED status
#
	mov.l	@(32,r14),r1     ! @(BASE + 32) => R1
	add	#1,r1            ! LP1(R1)++
	mov.l	r1,@(32,r14)     ! LP1(R1) => @(BASE + 32)
#
#    (E)Loop end
#
	bra	_main_s1         ! Loop end
	nop

#***************************************
#  3.Data area 
#***************************************
	.align 1
_PECRL1:
	.short	-11498           ! 0xFFFFFFFF - 11498 => 0xFFFFD316
_PECRL2:
	.short	-11500           ! 0xFFFFFFFF - 11500 => 0xFFFFD314
_PECRL3:
	.short	-11502           ! 0xFFFFFFFF - 11502 => 0xFFFFD312
_PECRL4:
	.short	-11504           ! 0xFFFFFFFF - 11504 => 0xFFFFD310
_PEIORL:
	.short	-11514           ! 0xFFFFFFFF - 11514 => 0xFFFFD306
_PEDRL:
	.short	-11518           ! 0xFFFFFFFF - 11518 => 0xFFFFD302
_PEPRL:
	.short	-11490           ! 0xFFFFFFFF - 11490 => 0xFFFFD31E
_RET_FF_S:
	.short	255

	.align 2
_RET_LPNUM_L: 
	.long	999999           ! PI_LOOP_NUM (long [32bit])