//****************************************************************************************** // Project : STM8S105C6T6 Sample Program // Program Name : // Programer : // Create date : Version 1.0 H24.10.08 // History : // Laungage : STM8Cosmic C Launguage //****************************************************************************************** // Description // OSC: Internal OSC 16MHz / External Clock 16MHz Crystal //****************************************************************************************** #include "iostm8s.h" void Init_clock_int(void); void Init_clock_ext(void); void WaitTIM(unsigned int); void Timer(void); int main(void) { unsigned char LEDlst=0; unsigned int lp; // ******************** // 1.Initialized // ******************** // (1)Define Clock // Init_clock_int(); //Internal OSC 16MHz Init_clock_ext(); //External OSC (16MHz Crystal) // (2)Define I/O PORT PB_DDR = 0b11111111; //Direction PB_CR1 = 0b11111111; //0:Open drain, 1:Push-pull PB_CR2 = 0b11111111; //0:Output speed up to 2 MHz, 1: Output speed up to 10 MHz // ******************** // 2.Main // ******************** LEDlst = 1; while(1){ if(LEDlst == 1){ LEDlst = 2; }else if(LEDlst > 127){ LEDlst = 1; }else{ LEDlst = LEDlst * 2; } PB_ODR = LEDlst; WaitTIM((unsigned int)10); } } //****************************************************************************************** // Function Name : Init_clock_int // Title : Initialized System clock // Input : // Output : // Description : Internal OSC 16MHz ( Default Clock : Internal OSC 2MHz) //****************************************************************************************** void Init_clock_int(void) { // ******************************* // Define CLK_CKDIVR (Clock divider register) Reset value: 0x18(0b00011000) // ******************************* // CLK_CKDIVR[7:5] Reserved, must be kept cleared. // CLK_CKDIVR[4:3] HSIDIV[1:0]: High speed internal clock prescaler // These bits are written by software to define the HSI prescaling factor. // 00: fHSI= fHSI RC output // 01: fHSI= fHSI RC output/2 // 10: fHSI= fHSI RC output/4 // 11: fHSI= fHSI RC output/8 // CLK_CKDIVR[2:0] CPUDIV[2:0]: CPU clock prescaler // These bits are written by software to define the CPU clock prescaling factor. // 000: fCPU=fMASTER // 001: fCPU=fMASTER/2 // 010: fCPU=fMASTER/4 // 011: fCPU=fMASTER/8 // 100: fCPU=fMASTER/16 // 101: fCPU=fMASTER/32 // 110: fCPU=fMASTER/64 // 111: fCPU=fMASTER/128 CLK_CKDIVR = 0b00000000; } //****************************************************************************************** // Function Name : Init_clock_ext // Title : Initialized System clock // Input : // Output : // Description : External Crystal OSC (16MHz) //****************************************************************************************** void Init_clock_ext(void) { // ******************************* // Define CLK_ECKCR (External clock register) Reset value: 0x00 // ******************************* // CLK_ECKR[7:2] Reserved, must be kept cleared. // CLK_ECKR[1] HSERDY: High speed external crystal oscillator ready // This bit is set and cleared by hardware. // 0: HSE clock not ready // 1: HSE clock ready (HSE clock is stabilized and available) // CLK_ECKR[0] HSEEN: High speed external crystal oscillator enable // This bit is set and cleared by software. // It can be used to switch the external crystal oscillator on or off. // 0: HSE clock off // 1: HSE clock on CLK_ECKCR = 0b00000001 ; while ((CLK_ECKCR & 0b00000010) == 0); // ******************************* // Define CLK_SWCR (Switch control register) // ******************************* // CLK_SWCR[7:4] Reserved. // CLK_SWCR[3] SWIF: Clock switch interrupt flag // CLK_SWCR[2] SWIEN: Clock switch interrupt enable // CLK_SWCR[1] SWEN: Switch start/stop // Writing a 1 to this bit enables switching the master clock to the source defined in the CLK_SWR register. // 0: Disable clock switch execution // 1: Enable clock switch execution // CLK_SWCR[0] SWBSY: Switch busy // This bit is set and cleared by hardware. It can be cleared by software to reset the clock switch process. // 0: No clock switch ongoing // 1: Clock switch ongoing CLK_SWCR = 0b00000010; // ******************************* // Define CLK_SWR (Clock master switch register) Reset value: 0xE1 // ******************************* // CLK_SWR[7:0] SWI[7:0]: Clock master selection bits // These bits are written by software to select the master clock source. // Its contents are write protected while a clock switch is ongoing (while the SWBSY bit is set). // They are set to the reset value (HSI) if the AUX bit is set in the CLK_CSSR register. // If Fast Halt wakeup mode is selected (FHW bit =1 in CLK_ICKR register) then these bits are set by hardware // to E1h (HSI selected) when resuming from Halt/Active-halt mode. // 0xE1: HSI selected as master clock source (reset value) // 0xD2: LSI selected as master clock source (only if LSI_EN option bit is set) // 0xB4: HSE selected as master clock source CLK_SWR = 0xB4 ; } //****************************************************************************************** // Function Name : WaitTIM // Title : // Input : // Output : // Description : //****************************************************************************************** void WaitTIM(unsigned int n) { unsigned int lp; for(lp=0;lp 10Hz(0.1S) //****************************************************************************************** void Timer(void) { // ********************************* // TIM1_CNTRH(Counter high) // TIM1_CNTRL(Counter low) // ********************************* // TIM1_CNTRH[7:0] CNT[15:8]: Counter value (MSB) // TIM1_CNTRL[7:0] CNT[7:0]: Counter value (LSB) TIM1_CNTRH = 0x00; TIM1_CNTRL = 0x00; // ********************************* // TIM1_PSCRH(Prescaler high) // TIM1_PSCRL(Prescaler low) // ********************************* // TIM1_PSCRH[7:0] PSC[15:8]: Prescaler value (MSB) // TIM1_PSCRL[7:0] PSC[7:0]: Prescaler value (LSB) // // 16[MHz] / 0d160[0xA0](Prescaler) ==> 100[KHz] // TIM1_PSCRH = 0x00; TIM1_PSCRL = 0xA0; // ********************************* // TIM1_ARRH(Auto-reload register high) // TIM1_ARRL(Auto-reload register low) // ********************************* // TIM1_ARRH[7:0]: ARR[15:8]: Auto-reload value (MSB) // TIM1_ARRL[7:0]: ARR[7:0]: Auto-reload value (LSB) // // 100KHz / 0d10000[0x2710](ARR) ==> 0.1[S] // TIM1_ARRH = 0x27; TIM1_ARRL = 0x10; // ********************************* // TIM1_CR1(Control register 1) Reset value: 0x00 // ********************************* // TIM1_CR1[7] ARPE: Auto-reload preload enable // TIM1_CR1[6:5] CMS[1:0]: Center-aligned mode selection // TIM1_CR1[4] DIR: Direction // 0: Counter used as up-counter // 1: Counter used as down-counter // TIM1_CR1[3] OPM: One-pulse mode // 0: Counter is not stopped at update event // 1: Counter stops counting at the next update event (clearing the CEN bit) // TIM1_CR1[2] URS: Update request source // TIM1_CR1[1] UDIS: Update disable. // TIM1_CR1[0] CEN: Counter enable // 0: Counter disabled // 1: Counter enabled TIM1_CR1 = 0b00000001; // ********************************* // TIM1_SR1(Status register 1) // ********************************* // TIM1_SR1[7] BIF: Break interrupt flag // TIM1_SR1[6] TIF: Trigger interrupt flag // TIM1_SR1[5] COMIF: Commutation interrupt flag // TIM1_SR1[4] CC4IF: Capture/compare 4 interrupt flag // TIM1_SR1[3] CC3IF: Capture/compare 3 interrupt flag // TIM1_SR1[2] CC2IF: Capture/compare 2 interrupt flag // TIM1_SR1[1] CC1IF: Capture/compare 1 interrupt flag // If channel CC1 is configured as output: // This flag is set by hardware when the counter matches the compare value, with some exception in // center-aligned mode (refer to the CMS bits from TIM1_CR1 register description). // It is cleared by software. // 0: No match // 1: The content of the counter register TIM1_CNT matches the content of the TIM1_CCR1 register // If channel CC1 is configured as input: // This bit is set by hardware on a capture. // It is cleared by software or by reading the TIM1_CCR1L register. // 0: No input capture has occurred // 1: The counter value has been captured in the TIM1_CCR1 register (an edge has been detected on // IC1 which matches the selected polarity). // TIM1_SR1[0] UIF: Update interrupt flag TIM1_SR1 &= 0b11111110; while((TIM1_SR1 & 0b00000001)==0); TIM1_CR1 &= 0b11111110; }